HD151TS206SS Datasheet, PDF (20/34 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)

HD151TS206SS
I²C Controlled Register Bit Map (cont.)
Byte27 Control Register
Bit
7
6
5
4
3
2
1
0
Note:
Description
Contents
Type
Reserved
R/W
PCIF_2 Skew Select Bit
0 = Normal, 1 = Late
R/W
PCIF_1 Skew Select Bit
0 = Normal, 1 = Late
R/W
PCIF_0 Skew Select Bit
0 = Normal, 1 = Late
R/W
3V66 Clock Skew Control
Delay
Ahead
R/W
Bit3
1000 = +0.0ns, 0111 = –0.5ns
3V66 Clock Skew Control
1001 = +0.5ns, 0110 = –1.0ns
R/W
Bit2
1010 = +1.0ns, 0101 = –1.5ns
3V66 Clock Skew Control
1011 = +1.5ns, 0100 = –2.0ns
R/W
Bit1
1100 = +2.0ns, 0011 = –2.5ns
3V66 Clock Skew Control
1101 = +2.5ns, 0010 = –3.0ns
R/W
Bit0
1110 = +3.0ns, 0001 = –3.5ns
1111 = +3.5ns, 0000 = –4.0ns
1. Normal = Skew1(B26[3:0]), Late = Skew1(B26[3:0]) + Skew2 (B26[7:4]).
Default
0
0
0
0
1
0
0
0
Note
See
Note1
Byte 28 Control Register
Bit Description
Contents
Type
7
Reserved
0 = Normal, 1 = Late
R/W
6
PCI_6 Skew Select Bit
0 = Normal, 1 = Late
R/W
5
PCI_5 Skew Select Bit
0 = Normal, 1 = Late
R/W
4
PCI_4 Skew Select Bit
0 = Normal, 1 = Late
R/W
3
PCI_3 Skew Select Bit
0 = Normal, 1 = Late
R/W
2
PCI_2 Skew Select Bit
0 = Normal, 1 = Late
R/W
1
PCI_1 Skew Select Bit
0 = Normal, 1 = Late
R/W
0
PCI_0 Skew Select Bit
0 = Normal, 1 = Late
R/W
Note: 1. Normal = Skew1(B26[3:0]), Late = Skew1(B26[3:0]) + Skew2 (B26[7:4]).
Default
0
0
0
0
0
0
0
0
Note
See
Note1
Byte29 Control Register
Bit Description
Contents
7
VCH Slew Rate Control Bit1 00 = Normal, 10 = “++”
6
VCH Slew Rate Control Bit0 ^{01 = “+“ , 11 = “–”}
5
PCI Slew Rate Control Bit1 00 = Normal, 10 = “++”
4
PCI Slew Rate Control Bit0 ^{01 = “+“ , 11 = “–”}
3
PCIF Slew Rate Control Bit1 00 = Normal, 10 = “++”
2
PCIF Slew Rate Control Bit0 ^{01 = “+“ , 11 = “–”}
1
3V66 Slew Rate Control Bit1 00 = Normal, 10 = “++”
0
3V66 Slew Rate Control Bit0 ^{01 = “+“ , 11 = “–”}
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
1
0
1
0
1
0
1
0
Note
Rev.1.00, Apr.28.2003, page 20 of 34