HD151TS206SS Datasheet, PDF (18/34 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)

HD151TS206SS
I²C Controlled Register Bit Map (cont.)
Byte23 Control Register
Bit Description
Contents
Type Default Note
7
Watchdog Enable Control Bit 0 = Disable, Pin22 = 3V66_0 output
R/W 0
1 = Enable, Pin22 = RESET# output
6
RESET# Reverse Control Bit 0 = Normal , 1 = Reverse
R/W 0
5
Watchdog Timer Count Bit3 These 4 bits corresponds to how many R/W 1
4
Watchdog Timer Count Bit2 ^{watchdog timer will wait from becoming} R/W 0
“Alarm mode” (B23[0] = 1) to outputting
3
Watchdog Timer Count Bit1 _{RESET# pin to “Low”.}
R/W 0
2
Watchdog Timer Count Bit0 ^{Default is 586ms x8 = 4.7s at Power}
R/W 0
ON
1
Backup Frequency Select Bit 0 = B10[4:0], 1 = B11[4:0]
R/W 0
When SAFE_F# is “Low” , frequency
mode is changed to the predefined
frequency mode decided by B10[4:0] or
B11[4:0].
0
Watchdog Status Bit
0 = Normal mode, 1 = Alarm mode
R/W 0
Byte24 Control Register
Bit Description
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Reserved
Contents
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Note
Rev.1.00, Apr.28.2003, page 18 of 34