HD151TS206SS Datasheet, PDF (7/34 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)

HD151TS206SS
I²C Controlled Register Bit Map
Byte0 Control Register
Bit Description
7 Reserved
6 Reserved
5 Reserved
4 Reserved
3 Reserved
2 Reserved
1 Reserved
0 Reserved
Contents
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
1
1
X
X
Note
Byte1 Control Register
Bit Description
7 Reserved
6 SRC Output enable
5 Reserved
4 Reserved
3 Reserved
2 CPU2 Output enable
1 CPU1 Output enable
0 CPU0 Output enable
Contents
0 = Disabled (tristate)
1 = Enabled
0 = Disabled (tristate)
1 = Enabled
0 = Disabled (tristate)
1 = Enabled
0 = Disabled (tristate)
1 = Enabled
Type
RW
RW
Default
0
1
Note
RW 1
RW 1
RW 1
RW 1
RW 1
RW 1
Byte2 Control Register
Bit Description
7
SRC_Pwrdwn drive mode
6
Reserved
5
CPU2_Pwrdwn drive mode
4
CPU1_Pwrdwn drive mode
3
CPU0_Pwrdwn drive mode
2
Reserved
1
Reserved
0
Reserved
Contents
0 = Driven in power down, 1 = Tristate
0 = Driven in power down, 1 = Tristate
0 = Driven in power down, 1 = Tristate
0 = Driven in power down, 1 = Tristate
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
0
0
0
0
0
Note
See
Table
2
See
Table
1
Rev.1.00, Apr.28.2003, page 7 of 34