HD151TS206SS Datasheet, PDF (15/34 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)

HD151TS206SS
I²C Controlled Register Bit Map (cont.)
Byte17 Control Register
Bit Description
Contents
Type
7
Reserved
1
R/W
6
Reserved
1
R/W
5
Reserved
1
R/W
4
PLL2 Output (VCO2)
0 = Normal mode
R/W
Frequency Control Bit
VCO2 frequency is changed on Table 5
(M2 / N2 Divider Control Bit) selection decided by FS4/3/2/1/0 or
PLL2 : for CPU
B9[5:1].
1 = Over or Down clocking mode
VCO2 frequency is changed by
B17[3:0] and B18[7:0] with decimal.
B17[3:0] and B18[7:0] are able to be
changed at B17[4] = 1.
3
VCO2 Frequency Control
These bits are 100MHz digit of VCO2 R/W
Bit11
frequency.
2
VCO2 Frequency Control
0000 = 0, 0001 = 1 …. 1001 = 9
R/W
Bit10
1
VCO2 Frequency Control
R/W
Bit9
0
VCO2 Frequency Control
R/W
Bit8
Note: 1. B17[3:0] and B18[7:0] must be written together (at writing B18) in every case.
Default
0
0
0
0
0
1
0
0
Note
See
Note1
Byte18 Control Register
Bit Description
Contents
Type
7
VCO2 Frequency Control
These bits are 10MHz digit of VCO2
R/W
Bit7
frequency.
6
VCO2 Frequency Control
0000 = 0, 0001 = 1 …. 1001 = 9
R/W
Bit6
5
VCO2 Frequency Control
R/W
Bit5
4
VCO2 Frequency Control
R/W
Bit4
3
VCO2 Frequency Control
These bits are 1MHz digit of VCO2
R/W
Bit3
frequency.
2
VCO2 Frequency Control
0000 = 0, 0001 = 1 …. 1001 = 9
R/W
Bit2
1
VCO2 Frequency Control
R/W
Bit1
0
VCO2 Frequency Control
R/W
Bit0
Note: 1. B17[3:0] and B18[7:0] must be written together (at writing B18) in every case.
Default
0
0
0
0
0
0
0
0
Note
See
Note1
Rev.1.00, Apr.28.2003, page 15 of 34