HD151TS206SS Datasheet, PDF (17/34 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)

HD151TS206SS
I²C Controlled Register Bit Map (cont.)
Byte20 Control Register
Bit Description
Contents
Type Default Note
7
VCO2 Frequency Read Bit7 Calculation result of VCO2 frequency. R
0
6
VCO2 Frequency Read Bit6 ^{1 MHz digit}
0000 = 0, 0001 = 1 …. 1001 = 9
5
VCO2 Frequency Read Bit5
R
0
R
0
4
VCO2 Frequency Read Bit4
R
0
3
VCO2 Frequency Read Bit3 Calculation result of VCO2 frequency. R
0
2
VCO2 Frequency Read Bit2 ^{0.1 MHz digit}
0000 = 0, 0001 = 1 …. 1001 = 9
1
VCO2 Frequency Read Bit1
R
0
R
0
0
VCO2 Frequency Read Bit0
R
0
Byte 21 Control Register
Bit Description
Contents
7
CPU Frequency Read Bit15 Calculation result of CPU frequency.
6
CPU Frequency Read Bit14 ^{100 MHz digit}
0000 = 0, 0001 = 1 …. 1001 = 9
5
CPU Frequency Read Bit13
4
CPU Frequency Read Bit12
3
CPU Frequency Read Bit11 Calculation result of CPU frequency.
2
CPU Frequency Read Bit10 ^{10MHz digit}
0000 = 0, 0001 = 1 …. 1001 = 9
1
CPU Frequency Read Bit9
0
CPU Frequency Read Bit8
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Note
Byte22 Control Register
Bit Description
7
CPU Frequency Read Bit7
6
CPU Frequency Read Bit6
5
CPU Frequency Read Bit5
4
CPU Frequency Read Bit4
3
CPU Frequency Read Bit3
2
CPU Frequency Read Bit2
1
CPU Frequency Read Bit1
0
CPU Frequency Read Bit0
Contents
Calculation result of CPU frequency.
1 MHz digit
0000 = 0, 0001 = 1 …. 1001 = 9
Calculation result of CPU frequency.
0.1 MHz digit
0000 = 0, 0001 = 1 …. 1001 = 9
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Note
Rev.1.00, Apr.28.2003, page 17 of 34