HD151TS206SS Datasheet, PDF (21/34 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)

HD151TS206SS
Clock Stop Timing Diagram
PWRDWN# Assertion/De-assersion
PWRDWN#
CPU (Stoppable)
CPU (Stoppable)
CPU# (Stoppable)
2× Iref (Controled by Byte2[5:3])
Float (Controled by Byte2[5:3])
Float
PWRDWN# Assertion/De-assertion Waveforms
< 1.8 ms
6× Iref
6× Iref
PWRDWN# Functionality
PWRDWN#
1
0
CPU
Normal
Iref:2
or Float
CPU# SRC
Normal Normal
Iref:2
Float _{or Float}
SRC#
Normal
Float
3V66 PCIF/PCI
66MHz 33MHz
Low
Low
USB/DOT
48MHz
Low
REF
14.318MHz
Low
Renasas clock generator I²C Serial Interface Operation
1. Write mode
1.1 Controller (host) sends a start bit.
1.2 Controller (host) sends the write address D2 (h).
1.3 Renasas clock generator will acknowledge (Renasas clock gen. sends “Low”).
1.4 Controller (host) sends a begin byte M.
1.5 Renasas clock generator will acknowledge (Renasas clock gen. sends “Low”).
1.6 Controller (host) sends a byte count N.
1.7 Renasas clock generator will acknowledge (Renasas clock gen. sends “Low”).
1.8 Controller (host) sends data from byte M to byte M+N–1.
1.9 Renasas clock generator will acknowledge each byte one at a time.
1.10 Controller (host) sends a stop bit.
1 bit
Start bit
7 bits
1 bit 1 bit
8 bits
1 bit
8 bits
1 bit 8 bits
Slave
address
R/W
D2(h)
Ack
Begin Byte = M
Ack Byte Count = N
Ack
Byte M
1 bit 8 bits 1 bit
Ack Byte M+1 Ack
8 bits
1 bit 1 bit
Byte M+N–1 Ack Stop bit
Rev.1.00, Apr.28.2003, page 21 of 34