HD151TS206SS Datasheet, PDF (10/34 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)

HD151TS206SS
I²C Controlled Register Bit Map (cont.)
Byte8 Read Back Byte Count Register
Bit Description
7
Read back byte count Bit7
6
Read back byte count Bit6
5
Read back byte count Bit5
4
Read back byte count Bit4
3
Read back byte count Bit3
2
Read back byte count Bit2
1
Read back byte count Bit1
0
Read back byte count Bit0
Contents
Writing to this register will configure
byte Count and how many bytes will be
read back.
Default is 1Ehex = 30 bytes.
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
1
1
1
1
0
Note
Byte9 Control Register
Bit Description
7
SSC2 Enable Bit
6
SSC1 Enable Bit
5
Clock Frequency Control
Bit4
4
Clock Frequency Control
Bit3
3
Clock Frequency Control
Bit2
2
Clock Frequency Control
Bit1
1
Clock Frequency Control
Bit0
0
Frequency Select Mode Bit
Contents
B6[2] = 0 or B9[7] = 1 : SSC2 = OFF
B6[2] = 1 & B9[7] = 0 : SSC2 = ON
B6[2] = 0 or B9[6] = 1 : SSC1 = OFF
B6[2] = 1 & B9[6] = 0 : SSC1 = ON
Latched input FS_4 at Power ON
Latched input FS_3 at Power ON
Latched input FS_2 at Power ON
Latched input FS_1 at Power ON
Latched input FS_0 at Power ON
0 = Freq. is selected by latched input
FS(4:0)
1 = Freq. is selected by I²C B9[5:1]
Type Default Note
RW 0
RW 0
RW X
RW X
See
Table3
RW X
RW X
RW X
RW 0
Rev.1.00, Apr.28.2003, page 10 of 34