HD151TS206SS Datasheet, PDF (6/34 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)

HD151TS206SS
Block Diagram
3.3 V VDD_48 VSS_48 3.3 V AVDD AVSS 6× 3.3V VDD 6×VSS
IREF
XTAL
14.318 MHz
OSC
PWRDWN#/SAFE_F#
VTT_PWRGD#
*MODE
*SEL100_200
*SEL66_48
*SEL48_24
*SEL33_25
*FS_4/3/2/1/0
SCLK
SDATA
CK2
1/M2
SSC2
1/N2
PLL2
For
CPU
VCO2
Input CK1 _1/M1
Clock
Select
SSC1
1/N1
PLL1
For
SRC
3V66
PCI
VCO1 ^Clock
Divider
CK0 _1/M0
1/N0
USB ^VCO0
PLL
Control Logic
Clock
Select
Delay
Control
Stop
Control
REF[1:0]
(14.318MHz)
CPU[2:0]
CPU[2:0]#
SRC
SRC#
PCI[5:0]
PCIF[2:0]
3V66_0/RESET#
3V66[2:1]
3V66_3/VCH
48MHz
48_24MHz
(*) : Latched Input pin.
Rev.1.00, Apr.28.2003, page 6 of 34