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HD151TS206SS Datasheet, PDF (22/34 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)
HD151TS206SS
Renasas clock generator I2C Serial Interface Operation (cont.)
2. Read mode
2.1 Controller (host) sends a start bit.
2.2 Controller (host) sends the write address D2 (h).
2.3 Renasas clock generator will acknowledge (Renasas clock gen. sends “Low”).
2.4 Controller (host) sends a begin byte M.
2.5 Renasas clock generator will acknowledge (Renasas clock gen. sends “Low”).
2.6 Controller (host) sends a restart bit.
2.7 Controller (host) sends the read address D3 (h).
2.8 Renasas clock generator will acknowledge (Renasas clock gen. sends “Low”).
2.9 Renasas clock generator will send the byte count N.
2.10 Controller (host) will acknowledge.
2.11 Renasas clock generator will send data from byte M to byte M+N–1.
2.12 When Renasas clock generator sends the last byte, controller (host) will not acknowledge.
2.13 Controller (host) sends a stop bit.
1 bit
Start bit
7 bits
1 bit 1 bit
8 bits
1 bit 1 bit
7 bits 1 bit
Slave
R/W Ack Begin Byte = M Ack Restart bit Slave
R/W
address D2(h)
address D3(h)
1 bit
8 bits
1 bit 8 bits 1 bit 8 bits 1 bit
Ack Begin Count = N Ack Byte M Ack Byte M+1 Ack
8 bits
1 bit 1 bit
Byte M+N–1 Not Ack Stop bit
Notes: 1.
2.
3.
4.
5.
6.
7.
Renasas clock generator is a slave/receiver, I2C component. It can read back the data stored in
the latches for the verification.
The data transfer rate supported by this clock generator is 100k bits/sec or less (standard
mode).
The input is operating at 3.3 V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only block-write from
the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The data is loaded until a stop sequence is
issued.
At power-on, all registers are set to a default condition, as shown.
Rev.1.00, Apr.28.2003, page 22 of 34