R-IN32M3_15 Datasheet, PDF (89/105 Pages) Renesas Technology Corp – LSI for Industrial Ethernet

R-IN32M3 Series Data Sheet
4. Electrical Specifications
4.7.5
Serial flash ROM interface
Parameter
SMSCK output cycle
SMSCK high level width
SMSCK low level width
SMSCK rise time
SMSCK fall time
SMSCK output delay time
SMCSZ output delay time
SMCSZ high level width
SMSI input setup time
SMSI input hold time
SMSI output delay time
SMSO input setup time
SMSO input hold time
SMSO output delay time
Symbol
tSFRCYC
tSMCKH
tSMCKL
tSMCKR
tSFRCYC
tDSMCSCK
tDSMCKCS
tSMCSH
tSSMI
tHSMI
tDSMI
tSSMO
tHSMO
tDSMO
Conditions
CL = 15pF
CL = 15pF
Freq = 50Mhz
CL = 15pF
Freq = 50MHz
CL = 15pF
-
-
CL = 15pF
-
-
CL = 15pF
MIN
MAX
Unit
20
-
ns
0.5 tSFRCYC - 2.0 0.5 tSFRCYC + 2.0 ns
0.5 tSFRCYC - 2.0 0.5 tSFRCYC + 2.0 ns
－
1.9
ns
－
7.5 ^Note
1.9
ns
－
ns
11.5 ^Note
－
ns
14 ^Note
6.0
0
-1.0
6.0
0
-1.0
－
ns
-
Ns
-
ns
5.0
ns
-
ns
-
ns
5.0
ns
Note Timing can be extended by setting of SFMSSC registor.
Please refer to 12.2.2 Chip Selection Control Register (SFMSSC)
of User’s Manual (Peripherals Function)
SMSCK（Output）
[SPI MODE 3]
SMSCK（Output）
[SPI MODE 0]
SMCSZ
（Output）
SMSO/SMSI
（Output）
SMSI/SMSO
（input）
< t_SFRCYC > < t_SMCKR >
< t_SMCKH >
< t_SMCKF >
< t_SMCKL >
< t_DSMCSCK >
< t_DSMI >
< t_DSMO >
MSB
< t_SSMO >
< t_SSMI>
MSB
< t_DSMCKCS > < t_SMCSH >
LSB
< t_HSMO >
< t_HSMI >
LSB
Figure 4.12Serial flash ROM access timing diagram
R18DS0008EJ0204
Dec 25, 2014
Page 89 of 100