R-IN32M3_15 Datasheet, PDF (57/105 Pages) Renesas Technology Corp – LSI for Industrial Ethernet

R-IN32M3 Series Data Sheet
3. Specifications
3.15 Asynchronous SRAM MEMC
Asynchronous SRAM MEMC can be connected to page ROM, ROM, SRAM or other peripheral device thar provides
a 16- or 32-bit SRAM interface.
Asynchronous SRAM MEMC’s signals are shared with the same ports used for synchronous burst access MEMC and
the External MPU interface; please set MEMCSEL and MEMIFSEL low to enable Asynchronous SRAM MEMC mode..
When BOOT0 is low and BOOT1 is high, the device will boot from memory connected to CSZ0.
3.15.1 Features
- Memory controller supporting page ROM, ROM, SRAM
- 32- or 16-bit data Bus
- Static memory control function
 Supports SRAM and peripheral devices with SRAM interface
 Page ROM support (supported STCSZ0 only)
 Four chip select signals are available (STCSZ0-STCSZ3)
STCSZ0 : page ROM / SRAM : 1000 0000H-13FF_FFFFH (64MByte)
STCSZ1 : SRAM only：1400 0000H-17FF_FFFFH (64MByte)
STCSZ2 : SRAM only：1800 0000H-1BFF_FFFFH (64MByte)
STCSZ3 : SRAM only：1C00 0000H-1FFF_FFFFH (64MByte)
- Programmable wait function
 Address setting wait
 Data wait
 Write recovery wait
 Idle state
R18DS0008EJ0204
Dec 25, 2014
Page 57 of 100