R-IN32M3_15 Datasheet, PDF (59/105 Pages) Renesas Technology Corp – LSI for Industrial Ethernet

R-IN32M3 Series Data Sheet
3. Specifications
3.17 Instruction RAM
Instruction RAM is 768Kbytes of memory that can be accessed from I-code AHB, D-code AHB, DMAC or an external
MPU.
3.17.1 Features
- 128-bit (32-bit x 4) read buffer
- Low latency :
 Read latency: 2 (1 for accessing read buffer)
 Write latency: 1
- 32-bit AHB Bus
- 128-bit RAM data bus width (without ECC circuit)
- Selectable 16- or 32-bit transfer size
- Burst transmission: single, imprecise burst, precise burst (INCR4/8/16, WRAP4/8/16)
- Little endian fixed
3.17.2 Read buffer features
- 128-bit (32bit x 4) read buffer
- Reply to AHB with 0 wait in cases of accessing read buffer
- Clear the data in the read buffer in case of 2-bit ECC error
- A 2-bit ECC error at the time of the read response generates an ECC error interrupt and treats it as an error
response of the AHB bus.
3.17.3 Write interface features
- 16-bit write access is supported; when two 16-bit words are written to IRAM, they are automatically merged into
a 32-bit word in the RAM.
- Error is generated on 8-bit write attempts
Caution Always ensure external host MPU writed 32-bits at a time.
R18DS0008EJ0204
Dec 25, 2014
Page 59 of 100