R-IN32M3_15 Datasheet, PDF (77/105 Pages) Renesas Technology Corp – LSI for Industrial Ethernet

R-IN32M3 Series Data Sheet
4. Electrical Specifications
4.7.3
External memory interface signals
(1) Delay value calculation method
The transition delay of the external memory interface pins depend on the capacirtive load driven, including both load
input pins and substrate / PCB capacitance. The table below shows how to calculate the delay based on capacitive load.
Drive capability
6mA
12mA
MIN.
0.026
0.012
Delay value per pF (ns)
MAX.
0.067
0.034
example）
When an address pin (6-mA output buffer) has 30-pF load, the actual delay is as follows.
MIN. 1.0ns(The MIN delay value at the time of 0 pF) + (0.026×30) ns = 1.78ns
MAX. 7.0ns(The MAX delay value at the time of 0 pF) + (0.067×30) ns = 9.01ns
(2) Asynchronous SRAM MEMC access timing
Parameter
Address, CSZ0-CSZ3 output delay time
RDZ output delay time
WRZ0 - WRZ3 (BENZ0-BENZ3), WRSTBZ
output delay time
BCYSTZ output delay time
WAITZ input setup time
WAITZ input hold time
Date input setup time
Data input hold time
Date output delay time
Data float delay time
Symbol
tDKA
tDKRD
tDKWR
tDKBSL
tSKW
tHKW
tSKID
tHKID
tDKOD
tHKOD
MIN
1.0
(1.78) ^Note
1.0
(1.78) ^Note
1.0
(1.78) ^Note
1.0
(1.78) ^Note
4.0
0
4.0
0
1.0
(1.78) ^Note
1.0
(1.78) ^Note
Note. Values in parenthesis are based on a 30pF capacitive load.
MAX
Unit
7.0
(9.01) ^Note
ns
7.0
(9.01) ^Note
ns
7.0
(9.01) ^Note
ns
7.0
(9.01) ^Note
ns
-
ns
-
ns
-
ns
-
ns
7.0
(9.01) ^Note
ns
7.0
(9.01) ^Note
ns
R18DS0008EJ0204
Dec 25, 2014
Page 77 of 100