R-IN32M3_15 Datasheet, PDF (41/105 Pages) Renesas Technology Corp – LSI for Industrial Ethernet

R-IN32M3 Series Data Sheet
3. Specifications
3.1.2
CPU Core Configuration
The Cortex-M3 included in R-IN32M3 has the following configuration.
Category
Process
Interrupts
Configuration Item
Process
NUM_IRQ
Interrupt Priority
LVL_WIDTH
Levels
MPU
MPU_PRESENT
Debug Level
DEBUG_LVL
Trace Level
TRACE_LVL
SW/SWJ-DP Select JTAG_PRESENT
Bit Band Area
BB_PRESENT
Setting
CB90-MR
128
4
Remark
Arbitrary value
Non-maskable Interrupt (NMI) + 1 to 240 physical
interrupts
Priority Bit Number 3 to 8 (8 to 256 priority levels)
Yes
3
2
SWJ-DP
Yes
Memory Protection is present
Debug Level 1 to 3
Trace Level 0 to 2
SWJ-DP selected in case of JTAG Access circuit
built-in.
Bit band function is present
Debug Level
Function outline
Debug Halt
Breakpoints
DWT comparator number
Flash patch function
1
Minimum Debug
configuration
Yes
2 (Instruction)
1 (Data Matching function:
unavailable)
No
2
Full Debug configuration
(Data Matching function:
unavailable)
Yes
6 (Instruction)
2 (Literal)
4 (Data Matching function:
unavailable)
Yes
3 (R-IN32M3’s setting)
Full Debug configuration
(Data Matching function:
available)
Yes
6 (Instruction)
2 (Literal)
4
Yes
Trace Level
Function outline
ITM, TPIU Function
DWT Trigger and Counter
ETM Function
0
Non-Trace
No
No
No
1
Standard Trace
Yes
Yes
No
2 (R-IN32M3’s setting)
Full Trace
Yes
Yes
Yes
Caution R-IN32M3 does not support SLEEPDEEP mode;
please do not set the SLEEPDEEP bit of the SCR register to “1”.
R18DS0008EJ0204
Dec 25, 2014
Page 41 of 100