R-IN32M3_15 Datasheet, PDF (18/105 Pages) Renesas Technology Corp – LSI for Industrial Ethernet

R-IN32M3 Series Data Sheet
2. Pin Information
2.3.3
External Memory Interface Signals
Pin Name
BUSCLK
CSZ0
CSZ1
CSZ2
CSZ3
A1
I/O
O
O
O
O
O
O
A2-A20
O
A21-A27
O
D0-D15^Note1
I/O
D16-D31 ^Note1
I/O
RDZ
O
WRSTBZ
O
WRZ0, WRZ1/ O
BENZ0, BENZ1
WRZ2, WRZ3/ O
BENZ2, BENZ3
WAITZ
I
WAITZ1-WAITZ3
Note2
BCYSTZ / ADVZ O
Note3
Function
Bus clock output port
Chip select signal output
port
Address output port
Data bus port
Read strobe output port
Write strobe output port
Effectively Byte lane strobe
output port
Wait signal input port
Shared Signal
-
HCSZ
HPGCSZ
-
-
HA1
Shared
port
-
-
P44
P51
P50
P40
HA2-HA20
-
-
RP21-
RP27
HD0-HD15
-
HD16-HD31
RP30-
RP37
RP10-
RP17
HRDZ
-
HWRSTBZ
-
HWRZ0, HWRZ1/ -
HBENZ0, HBENZ1
HWRZ2, HWRZ3/ RP06，
HBENZ2, HBENZ3 RP07
HWAITZ
P41
-
P45-P47
Active
-
Low
-
-
Low
Low
Low
Low
Level during reset
-
Hi-Z
With internal
pull-up resistor
Hi-Z
With internal
pull-up resistor
Hi-Z
With internal
pull-down resistor
Hi-Z
With internal
pull-up resistor
Hi-Z
With internal
pull-up resistor
Hi-Z
With internal
pull-up resistor
Address valid output port HBCYSTZ
RP20
Low
Hi-Z
With internal
pull-up resistor
Remark External Memory Interface Signal expects BUSCLK is an input signal while the internal reset
signal (HRESETZ) is active.
Note1. When using synchronous burst access MEMC this port is shared with Address port when
ADMUXMODE is high.
Note2. This port is available only when using synchronous burst access MEMC.
Note3. This port functions as BCYSTZ when using asynchronous SRAM MEMC, it functions as ADVZ
when using synchronous burst access MEMC
R18DS0008EJ0204
Dec 25, 2014
Page 18 of 100