R-IN32M3_15 Datasheet, PDF (58/105 Pages) Renesas Technology Corp – LSI for Industrial Ethernet

R-IN32M3 Series Data Sheet
3. Specifications
3.16 Synchronous burst access MEMC
The Synchronous burst access MEMC can be connected to page ROM, ROM, SRAM, PSRAM, NOR-Flash and other
peripheral devices which provide a 16- or 32-bit SRAM interface.
It can also support multiplexed address/data signals when ADMUXMODE pin is set high.
Synchronous burst access MEMC’s signals are shared with the same ports used for asynchronous SRAM MEMC and
External MPU interface; please set MEMCSEL high and MEMIFSEL low to enable synchronous burst access MEMC
mode.
When BOOT0 is low and BOOT1 is high, the device will boot from memory connected to CSZ0.
3.16.1 Features
- Memory controller supports page ROM, ROM, SRAM (sync or async), PSRAM and NOR-Flash
- 32- or 16-bit data Bus
- Address / data multiplex option
Remark Page access is supported in async access mode only.
- Static memory control function
 SRAM (sync or async) and other peripheral devices which provide a 16- or 32-bit SRAM interface
 Four chip select signals is available (CSZ0-CSZ3)
CSZ0 : 1000 0000H-13FF_FFFFH (64MByte)
CSZ1 : 1400 0000H-17FF_FFFFH (64MByte)
CSZ2 : 1800 0000H-1BFF_FFFFH (64MByte)
CSZ3 : 1C00 0000H-1FFF_FFFFH (64MByte)
Remark Each CS can be set between 1000_0000H - 1FFF_FFFFH by the programmable SMADSEL
register .
- Programmable wait setting functions
 Data wait
 Write recovery wait
 Idle state
- Memory access frequency option (by dividing 100MHz signal by 2 to 6 )
- Up to four wait state signals available (WAITZ0 - WAITZ3)
R18DS0008EJ0204
Dec 25, 2014
Page 58 of 100