R-IN32M3_15 Datasheet, PDF (79/105 Pages) Renesas Technology Corp – LSI for Industrial Ethernet

R-IN32M3 Series Data Sheet
(b) Write timing
4. Electrical Specifications
BUSCLK (output)
< t_DKA >
A1-A26 (output)
CSZ0-CSZ3
(output)
WRZ0-WRZ3^note, WRSTB (output)
< tDKA >
< t_DKWR
>
< tDKWR
>
BEZ0-BEZ3^note (output)
< tDKA >
< t_DKWR
>
< t_DKWR
>
RDZ (output)
< t_DKOD >
< t_HKOD >
D0-D31 (i/o)
WAITZ (input)
< t_HKW >
< t_SKW >
< t_DKBS > ^{< tDKBS >}
BCYSTZ (input)
< t_DKOD >
Figure 4.5 Memory controller read timing diagram (asynchronous memory)
Note. WRZ0-WRZ3 and BENZ0-BENZ3 serve dual purposes; The function is selected by the WREN
registers.
Remark. The timing diagram in Figure 4.4 shows the case for when “Idle Wait”, “Write Recovery Wait”,,
and “Address Wait” are set to 0, and “Data Wait” is set to 3.
R18DS0008EJ0204
Dec 25, 2014
Page 79 of 100