H8S2117R Datasheet, PDF (862/1024 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 25 Clock Pulse Generator
Table 25.3 External Clock Input Conditions
Item
Symbol
External clock input pulse t
EXL
width low level
External clock input pulse t
EXH
width high level
External clock rising time t
EXr
External clock falling time t
EXf
Clock pulse width low level t
CL
Clock pulse width high level t
CH
VCC = 3.0 to 3.6 V
Min.
Max.
20

Unit Test Conditions
ns Figure 25.5
20

ns

5
ns

5
ns
0.4
0.6
t
Figure 28.4
cyc
0.4
0.6
t
cyc
t_EXH
t_EXL
EXTAL
V_CC × 0.5
t_EXr
t_EXf
Figure 25.5 External Clock Input Timing
The oscillator and duty correction circuit can adjust the waveform of the external clock input that
is input from the EXTAL pin.
When a specified clock signal is input to the EXTAL pin, internal clock signal output is
determined after the external clock output stabilization delay time (t_DEXT) has passed. As the clock
signal output is not determined during the t_DEXT cycle, a reset signal should be set to low to
maintain the reset state. Table 25.4 shows the external clock output stabilization delay time. Figure
25.6 shows the timing of the external clock output stabilization delay time.
Rev. 1.00 Apr. 28, 2008 Page 836 of 994
REJ09B0452-0100