H8S2117R Datasheet, PDF (260/1024 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 9 14-Bit PWM Timer (PWMX)
In this example, DADR = H'0207 (B'0000 0010 0000 0111). The output waveform is shown in
figure 9.7. Since CFS = 1 and the value of the upper eight bits is B'0000 0010, the high width of
the base pulse duty cycle is 2/256 × (T).
Since the value of the subsequent six bits is B'0000 01, an additional pulse is output only at the
location of base pulse No. 63 according to table 9.6. Thus, an additional pulse of 1/256 × (T) is to
be added to the base pulse.
Base cycle
No. 0
1 conversion cycle
Base cycle
No. 1
Base cycle
No. 63
Base pulse
High width: 2/256 × (T)
Base pulse
2/256 × (T)
Additional pulse output location
Additional pulse
1/256 × (T)
Figure 9.7 Output Waveform when DADR = H'0207 (OS = 1)
However, when CFS = 0 (base cycle = resolution (T) × 64), the duty cycle of the base pulse is
determined by the upper six bits and the locations of the additional pulses by the subsequent eight
bits with a method similar to as above.
Rev. 1.00 Apr. 28, 2008 Page 234 of 994
REJ09B0452-0100