H8S2117R Datasheet, PDF (790/1024 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 24 Flash Memory
(6) Flash Transfer Destination Address Register (FTDAR)
FTDAR specifies the start address of the on-chip RAM at which to download an on-chip program.
FTDAR must be set before setting the SCO bit in FCCS to 1.
Initial
Bit
Bit Name Value R/W Description
7
TDER 0
R/W Transfer Destination Address Setting Error
This bit is set to 1 when an error has occurred in setting
the start address specified by bits TDA6 to TDA0.
A start address error is determined by whether the value
set in bits TDA6 to TDA0 is within the range of H'00 to
H'01 when download is executed by setting the SCO bit
in FCCS to 1. Make sure that this bit is cleared to 0
before setting the SCO bit to 1 and the value specified
by bits TDA6 to TDA0 should be within the range of
H'00 to H'01.
0: The value specified by bits TDA6 to TDA0 is within
the range.
1: The value specified by bits TDA6 to TDA0 is between
H'02 and H'FF and download has stopped.
6
TDA6 0
R/W Transfer Destination Address
5
TDA5 0
4
TDA4 0
3
TDA3 0
2
TDA2 0
1
TDA1 0
0
TDA0 0
R/W Specifies the on-chip RAM start address of the
R/W
download destination. A value between H'00 and H'01,
R/W
and up to 3 kbytes can be specified as the start address
of the on-chip RAM.
R/W
H'00:
H'FFD080 is specified as the start
R/W
address.
R/W
H'01:
H'FFD880 is specified as the start
address.
H'02 to H'7F: Setting prohibited.
(Specifying a value from H'02 to H'7F sets
the TDER bit to 1 and stops download of
the on-chip program.)
Rev. 1.00 Apr. 28, 2008 Page 764 of 994
REJ09B0452-0100