H8S2117R Datasheet, PDF (797/1024 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 24 Flash Memory
(c) Erasure
FPFR indicates the return value of the erasure result.
Initial
Bit
Bit Name Value R/W Description
7



Unused
Returns 0.
6
MD

R/W Erasure Mode Related Setting Error Detect
Detects the error protection state and returns the result.
When the error protection state is entered, this bit is set
to 1. Whether the error protection state is entered or not
can be confirmed with the FLER bit in FCCS. For
conditions to enter the error protection state see section
24.9.3, Error Protection.
0: Normal operation (FLER = 0)
1: Error protection state, and programming cannot be
erased (FLER = 1)
5
EE

R/W Erasure Execution Error Detect
Returns 1 when the user MAT could not be erased or
when the flash memory related register settings are
partially changed. If this bit is set to 1, there is a high
possibility that the user MAT has been erased partially.
In this case, after removing the error factor, erase the
user MAT. Also an attempt to erase the user MAT when
the FMATS value is H'AA and the user boot MAT is
selected leads to an erasure execution error. In that
case, both the user MAT and user boot MAT are not
erased. Erasure of the user boot MAT must be
performed in boot mode or programmer mode.
0: Erasure has ended normally
1: Erasure has ended abnormally
4
FK

R/W Flash Key Register Error Detect
Checks the FKEY value (H'5A) before erasure starts,
and returns the result.
0: FKEY setting is normal (H'5A)
1: FKEY setting is abnormal (value other than H'5A)
Rev. 1.00 Apr. 28, 2008 Page 771 of 994
REJ09B0452-0100