H8S2117R Datasheet, PDF (610/1024 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 18 I²C Bus Interface (IIC)
Table 18.11 I²C Bus Timing (with Maximum Influence of t_Sr/t_Sf)
Time Indication (at Maximum Transfer Rate) [ns]
Item
t_SCLHO
t_cyc Indication
t_Sr/t_Sf
I²C Bus
Influence Specification
(Max.) (Min.)
0.5 t_SCLO (–t_Sr) Standard mode –1000 4000
High-speed mode –300
600
φ=
8 MHz
4000
950
φ=
φ=
φ=
10 MHz 16 MHz 20 MHz
4000 4000 4000
950
950
950
t_SCLLO
0.5 t_SCLO (–t_Sf) Standard mode –250
High-speed mode –250
4700
1300
4750
1000*¹
4750
1000*¹
4750
1000*¹
4750
1000*¹
t_BUFO
0.5 t_SCLO –1 t_cyc Standard mode –1000
4700
(–t_Sr)
High-speed mode –300
1300
3875*¹
825*¹
3900*¹
850*¹
3939*¹
888*¹
3950*¹
900*¹
t_STAHO
0.5 t_SCLO –1 t_cyc Standard mode –250
(–t_Sf)
High-speed mode –250
4000
600
4625
875
4650
900
4688
938
4700
900
t_STASO
1 t_SCLO (–t_Sr)
Standard mode –1000
High-speed mode –300
4700
600
9000
2200
9000
2200
9000
2200
9000
2200
t_STOSO
0.5 t_SCLO + 2 t_cyc Standard mode –1000
(–t_Sr)
High-speed mode –300
4000
600
4250
1200
4200
1150
4125
1075
4100
1050
t_SDASO
1
t *3
SCLLO
–3
t_cyc
Standard mode
–1000
250
(master) (–t_Sr)
High-speed mode –300
100
3325
625
3400
700
3513
813
3550
850
t_SDASO
(slave)
1
t *3
SCLL
–12 t_cyc*²
(–t_Sr)
Standard mode –1000 250
High-speed mode –300
100
2200 2500 2950 3100
–500*¹ –200*¹ 250
400
t_SDAHO
3 t_cyc
Standard mode 0
0
375
300
188
150
High-speed mode 0
0
375
300
188
150
Notes: 1. Does not meet the I²C bus interface specification. Remedial action such as the following
is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and
fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate;
(d) select slave devices whose input timing permits this output timing.
The values in the above table will vary depending on the settings of the IICX bit and bits
CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the
maximum transfer rate; therefore, whether or not the I²C bus interface specifications are
met must be determined in accordance with the actual setting conditions.
2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (t –
SCLL
6 t ).
cyc
3. Calculated using the I²C bus specification values (standard mode: 4700 ns min.; high-
speed mode: 1300 ns min.).
Rev. 1.00 Apr. 28, 2008 Page 584 of 994
REJ09B0452-0100