H8S2117R Datasheet, PDF (729/1024 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 21 FSI Interface
21.4 Operation
21.4.1 LPC/FW Memory Cycles
In LPC/FW memory read and write cycles, data is transferred using LAD3 to LAD0
synchronously with LCLK. The order of data transfer is shown in table 21.4. In a cycle returning
synchronization signal from the slave, the slave usually returns B'1010 to notify the host of error
occurrence; while the FSI in this LSI always returns B'0000 (Ready) or B'0110 (Long wait).
The FSI becomes busy if the received address matches an address in the host accessible range set
in the registers (FSIHBARH, FSIHBARL, FSISR, and CMDHBAR), and outputs a turn-around
signal to return to the idle state.
Table 21.4 LPC Memory Read/Write Cycles
State
LPC Memory Read Cycles
Counts Content
Driven by Value (3 to 0)
1
Start
Host
0000
2
Cycle type/ Host
direction
0100
3
Address 1 Host
bit 31 to bit 28
4
Address 2 Host
bit 27 to bit 24
5
Address 3 Host
bit 23 to bit 20
6
Address 4 Host
bit 19 to bit 16
7
Address 5 Host
bit 15 to bit 12
8
Address 6 Host
bit 11 to bit 8
9
Address 7 Host
bit 7 to bit 4
10
Address 8 Host
bit 3 to bit 0
11
Turn-around Host
(recovery)
1111
12
Turn-around None
ZZZZ
13
Wait*
Slave
0110
LPC Memory Write Cycles
Content
Driven by Value (3 to 0)
Start
Host
0000
Cycle type/
direction
Host
0110
Address 1
Host
bit 31 to bit 28
Address 2
Host
bit 27 to bit 24
Address 3
Host
bit 23 to bit 20
Address 4
Host
bit 19 to bit 16
Address 5
Host
bit 15 to bit 12
Address 6
Host
bit 11 to bit 8
Address 7
Host
bit 7 to bit 4
Address 8
Host
bit 3 to bit 0
Data 1
Host
bit 3 to bit 0
Data 2
Turn-around
(recovery)
Host
Host
bit 7 to bit 4
1111
Rev. 1.00 Apr. 28, 2008 Page 703 of 994
REJ09B0452-0100