H8S2117R Datasheet, PDF (329/1024 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
10.8.11 Conflict between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T₂ state of a TCNT write cycle, and
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set. Figure 10.52 shows the operation timing when there is conflict between TCNT write and
overflow.
TCNT write cycle
T1
T2
φ
Address
TCNT address
Write signal
TCNT
H'FFFF
TCNT write data
M
TCFV flag
Figure 10.52 Conflict between TCNT Write and Overflow
10.8.12 Multiplexing of I/O Pins
In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin
with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input
pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not
be performed from a multiplexed pin.
10.8.13 Module Stop Mode Setting
TPU operation can be enabled or disabled by the module stop control register. In the initial state,
TPU operation is disabled. Access to TPU registers is enabled when module stop mode is
cancelled. For details, see section 26, Power-Down Modes.
Rev. 1.00 Apr. 28, 2008 Page 303 of 994
REJ09B0452-0100