H8S2117R Datasheet, PDF (633/1024 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

19.4.7 Receive Timing
Figure 19.12 shows the receive timing.
Section 19 Keyboard Buffer Control Unit (PS2)
φ*
KCLK (pin)
KD (pin)
Internal
KCLK (KCLKI)
Falling edge
signal
RXCR3 to
RXCR0
N
N+1
N+2
Internal KD
(KDI)
KBBR7 to
KBBR0
Note: * φ here indicates the clock signal frequency-divided by N for medium-speed mode.
Figure 19.12 Receive Counter and KBBR Data Load Timing
19.4.8 Operation during Data Reception
If the KBS bit in KBCRH is set to 1 with other keyboard buffer control units in reception*, the
KCLK is automatically pulled down. Figure 19.13 shows receive timing and the KCLK.
Note: * Period from the first falling edge of KCLK to completion of reception (KBF = 1).
KCLK
1
2
8
9
10
11
Automatic I/O inhibit
KD
Start bit
0
1
7
Parity
Stop bit
KBF
KCLK for
other PS/2
Figure 19.13 Receive Timing and KCLK
Rev. 1.00 Apr. 28, 2008 Page 607 of 994
REJ09B0452-0100