H8S2117R Datasheet, PDF (147/1024 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 5 Interrupt Controller
5.6.2 Interrupt Control Mode 1
In interrupt control mode 1, mask control is applied to three levels for interrupt requests other than
NMI and address break by comparing the I and UI bits in CCR in the CPU, and the ICR setting.
• An interrupt request with interrupt control level 0 is accepted when the I bit in CCR is cleared
to 0. When the I bit is set to 1, the interrupt request is held pending.
• An interrupt request with interrupt control level 1 is accepted when the I bit or UI bit in CCR is
cleared to 0. When both the I and UI bits are set to 1, the interrupt request is held pending.
For instance, the state transition when the interrupt enable bit corresponding to each interrupt is set
to 1, and ICRA to ICRD are set to H'20, H'00, H'00, and H'00, respectively (IRQ2 and IRQ3
interrupts are set to interrupt control level 1, and other interrupts are set to interrupt control level
0) is shown below. Figure 5.8 shows a state transition diagram.
• All interrupt requests are accepted when I = 0. (Priority order: NMI > IRQ2 > IRQ3 > address
break > IRQ0 > IRQ1 …)
• Only NMI, IRQ2, IRQ3, and address break interrupt requests are accepted when I = 1 and UI =
0.
• Only NMI and address break interrupt requests are accepted when I = 1 and UI = 1.
All interrupt requests
are accepted
I0
I 1, UI 0
Only NMI, address break, and
interrupt control level 1 interrupt
requests are accepted
Exception handling execution
or I 1, UI 1
I0
UI 0
Only NMI and address break
interrupt requests are accepted
Exception handling
execution or UI 1
Figure 5.8 State Transition in Interrupt Control Mode 1
Rev. 1.00 Apr. 28, 2008 Page 121 of 994
REJ09B0452-0100