H8S2117R Datasheet, PDF (499/1024 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 16 CIR Interface
Initial
Bit
Bit Name
Value R/W Description
3
REPRCVE 0
R/W Receive Enable after Repeat Detection
Enables/disables the CIR reception after a repeat
detection.
0: The CIR reception is disabled by a repeat
detection.
1: The CIR reception is enabled by a repeat detection
2

0
R/W Reserved
The initial value should not be changed.
1
CLK1
0
R/W Reference Clock
0
CLK0
0
R/W 00: Internal clock φ
01: Internal clock φ/2
10: Internal clock φ/4
11: subclock φsub
16.3.2 Receive Control Register 2 (CCR2)
CCR2 consists of the bits that select the CIR communication format.
Bit
Bit Name
7
TFM1
6
TFM0
5 to 0 
Initial
Value R/W Description
0
R/W Reception Signal Format Select
0
R/W 00: NEC format (4 bytes are used)
(Address, address, command, and command are
stored in CIRRDR.)
01: NEC format (2 bytes are used)
(Address and command are stored in CIRRDR.)
10: Setting prohibited
11: Setting prohibited
All 0
R/W Reserved
The initial value should not be changed.
Rev. 1.00 Apr. 28, 2008 Page 473 of 994
REJ09B0452-0100