RZT1_15 Datasheet, PDF (4/52 Pages) Renesas Technology Corp – 450 MHz/600MHz, MCU with ARM Cortex®-R4F

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RZ/T1 Group
1. Overview
Table 1.1
Outline of Specifications (3 / 7)
Classification
Timers
Module/Function
Description
16-bit timer pulse unit
(TPUa)
 (16 bits × 6 channels) × 2 units*¹
 Maximum of 32 pulse-input/output possible
 Select from among seven or eight counter-input clock signals for each channel
(with maximum operating frequency of 75 MHz)
 Input capture/output compare function
 Counter clear operation (synchronous clearing by compare match/input capture)
 Simultaneous writing to multiple timer counters (TCNT)
 Simultaneous register input/output by synchronous counter operation
 Output of PWM waveforms in up to 15 phases in PWM mode
 Support for buffered operation, phase-counting mode (two phase encoder input) and
cascade-connected operation (32 bits × 2 channels) depending on the channel.
 PPG output trigger can be generated
 Capable of generating conversion start triggers for the A/D converters
 Digital noise filtering of signals from the input capture pins
 Event linking by the ELC
Multifunction timer pulse
unit (MTU3a)
 9 channels (16 bits × 8 channels, 32 bits × 1 channel)
 Maximum of 28 pulse-input/output and 3 pulse-input possible
 Select from among 9, 11, or 12 counter-input clock signals for each channel
(with maximum operating frequency of 150 MHz)
 Input capture function
 39 output compare/input capture registers
 Counter clear operation (synchronous clearing by compare match/input capture)
 Simultaneous writing to multiple timer counters (TCNT)
 Simultaneous register input/output by synchronous counter operation
 Buffered operation
 Support for cascade-connected operation
 Automatic transfer of register data
 Pulse output mode
Toggle/PWM/complementary PWM/reset-synchronized PWM
 Complementary PWM output mode
Outputs non-overlapping waveforms for controlling 3-phase inverters
Automatic specification of dead times
PWM duty cycle: Selectable as any value from 0% to 100%
Delay can be applied to requests for A/D conversion.
Non-generation of interrupt requests at peak or trough values of counters can be
selected.
Double buffer configuration
 Reset synchronous PWM mode
Three phases of positive and negative PWM waveforms can be output with desired
duty cycles.
 Phase-counting mode: 16-bit mode (channels 1 and 2); 32-bit mode (channels 1 and 2)
 Counter functionality for dead-time compensation
 Generation of triggers for A/D converter conversion
 A/D converter start triggers can be skipped
 Digital noise filter function for signals on the input capture and external counter clock
pins
 PPG output trigger can be generated
 Event linking by the ELC
R01DS0228EJ0070 Rev.0.70
Dec 25, 2014
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