RZT1_15 Datasheet, PDF (35/52 Pages) Renesas Technology Corp – 450 MHz/600MHz, MCU with ARM Cortex®-R4F

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RZ/T1 Group
1. Overview
Table 1.7
List of Pin and Pin Functions (320-Pin FBGA) (2 / 10)
Pin
Number
320-Pin
FBGA
Power
Supply
Clock
System
Contro
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
AVSS0
B17
AVSS1
B18
VREFL1
B19
B20
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
I/O Port Bus
PB2
PC1
PB7
P86
PD7
P52
Timer
(MTU3a, GPTa,
TPUa, PPG, POE3,
CMTW)
MTIOC1A
MTIOC3B /
GTIOC0A / TOC3
MTIOC4B /
GTIOC2A / TOC1
MTIOC4D /
GTIOC2B / TOC0
Communication
(ETHERC,
ECATC*¹, SCIFA,
RSPIa, RIICa,
RSCAN, SPIBSC,
USB)
ETH1_RXC /
ETH0_RXD1 /
CATSYNC1 /
CATLATCH1 /
SSL30
ETH1_RXD3 /
PHYLINK0 / SDA1
ETH1_RXD1
ETH1_TXD0 /
RSPCK2
ETH1_TXD1
ETH0_INT / SSL20
P16
CS4# /
MTIOC3B /
CS2#
GTIOC0A
P15
CS3# / CKE MTIOC3D /
GTIOC0B
PJ7
ETH0_RXD3 /
CATLEDRUN /
CTS3#
PJ6
ETH0_RXD2 /
CATIRQ / SCK3
PU2
TIOCD9
ETH2_CRS / RXD3
PL7
ETH2_RXDV
PL5
TIOCA8
ETH2_RXD2
PB6
TCLKA
ETH_MDC / SCK3 /
RTS4# / MISO3
PB3
CS1#
ETH1_CRS /
PHYRESETOUT# /
TXD3 / CTXD1
PB1
MTCLKA / TCLKC ETH1_RXER /
CTS4#
PF5
MTIOC4A /
ETH1_TXEN
GTIOC1A / TIC2
P87
A23
MTIOC4C /
GTIOC1B
ETH1_TXC /
ETH0_RXD0
PD6
A22
TIC1
ETH1_TXD2 /
ETH0_TXD1 /
MISO2
P53
ETH1_INT / MISO2
P51
PHYLINK1 /
RSPCK2
Others
(SSI, DSMIF)
MDAT1
MDAT2
MCLK0
MCLK1
MCLK2
Interrupt
IRQ9
IRQ15
IRQ14
IRQ2
IRQ15
IRQ3
IRQ1
S12ADC
AN1_ANE
X0
AN115
AN006
AN003
AN001
AN1_ANE
X1
AN114
AN004
R01DS0228EJ0070 Rev.0.70
Dec 25, 2014
Page 35 of 52