RZT1_15 Datasheet, PDF (2/52 Pages) Renesas Technology Corp – 450 MHz/600MHz, MCU with ARM Cortex®-R4F

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RZ/T1 Group
1. Overview
1. Overview
1.1 Outline of Specifications
This LSI circuit is a high-performance MCU equipped with the ARM Cortex^®-R4F processor and Cortex-M3 (for
products incorporating an R-IN engine) processors, and incorporating integrated peripheral functions necessary for
system configuration. Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of
products in different packages.
Table 1.1 shows the outline of maximum specifications, and the number of peripheral module channels differs
depending on the pin number on the package. For details, see Table 1.2, Comparison of Functions for Different
Packages.
Table 1.1
Outline of Specifications (1 / 7)
Classification
CPU
Module/Function
Central processing unit
(Cortex-R4F)
Central processing unit
(Cortex-M3)
(for products
incorporating an R-IN
engine)
FPU
(Cortex-R4F)
Memory
On-chip extended
SRAM with ECC
Operating modes
Clock
Clock generation circuit
Reset
Description
 Maximum operating frequency
320-pin FBGA: 600 MHz
176-pin HLQFP: 450 MHz
 32-bit CPU Cortex-R4F designed by ARM (core revision r1p4)
 Address space: 4 Gbytes
 Instruction cache: 8 Kbytes (with ECC with)
 Data cache: 8 Kbytes (with ECC with)
 Tightly coupled memory (TCM)
ATCM: 512 Kbytes (with ECC with)
BTCM: 32 Kbytes (with ECC with)
 Instruction set: ARMv7-R architecture, so support includes Thumb and Thumb-2
 Data arrangement
Instructions: Little endian
Data: Little endian
 Memory protection unit (MPU)
 Operating frequency: 150 MHz
 32-bit CPU Cortex-M3 designed by ARM (core revision r2p1)
 Address space: 4 Gbytes
 Instruction set: ARMv7-R architecture, so support includes Thumb® and Thumb-2
 Data arrangement
Instructions: Little endian
Data: Little endian
 Memory protection unit (MPU)
 Supports addition, subtraction, multiplication, division, multiply-and-accumulate, and
square-root operations at single- and double-precision.
 Registers
32-bit single-word registers: 32 bits ×32
(can be used as 16 double-word registers: 64 bits x 16)
 Capacity: Up to 1 Mbyte
 150 MHz
 SEC-DED (single error correction/double error detection)
 Three boot modes
SPI boot mode (for booting up from serial flash memory)
16-bit bus boot mode (NOR Flash)
32-bit bus boot mode (NOR Flash)
 The input clock can be selected from an external clock signal or external resonator.
 Detection of input clock oscillation stopping
 The following clocks are generated.
CPU clock: 450/600 MHz (max.)
System clock: 150 MHz (fixed)
High-speed peripheral module clock: 150 MHz (fixed)
Low-speed peripheral module clock: 75 MHz (fixed)
ADCCLK in the 12-bit A/D converter (S12ADC): 60 MHz (max.)
External bus clock: 75 MHz (max.)
Low-speed on-chip oscillator: 240 kHz (fixed)
RES # pin reset, error control module (ECM) reset, software reset
R01DS0228EJ0070 Rev.0.70
Dec 25, 2014
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