RZT1_15 Datasheet, PDF (3/52 Pages) Renesas Technology Corp – 450 MHz/600MHz, MCU with ARM Cortex®-R4F

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RZ/T1 Group
1. Overview
Table 1.1
Outline of Specifications (2 / 7)
Classification
Low power
Interrupt
External bus
extension
Data transfer
I/O ports
Module/Function
Description
Low power consumption  Standby mode (Cortex-R4F)
 Sleep mode (Cortex-M3) (for products incorporating an R-IN engine)
 Module stop function
Cortex-R4F
vector interrupt
controller (VIC)
 Peripheral function interrupts: 272 sources / 274 sources (for products incorporating an
R-IN engine)
 External interrupts: 20 sources
(NMI, IRQ0 to IRQ15, ETH0_INT, ETH1_INT, and ETH2_INT pins)
 Software interrupts: 1 source
 Non-maskable interrupts: 2 sources
 Sixteen levels specifiable for the order of priority
Cortex-M3 nested-type
vector interrupt
controller (NVIC)
(only included in
products incorporating
an R-IN engine)
 Peripheral function interrupts: 82 sources
 External interrupts: 19 sources
(IRQ0 to IRQ15, ETH0_INT, ETH1_INT, and ETH2_INT pins)
 Software interrupts: 1 source
 Non-maskable interrupts: 1 source
 Sixteen levels specifiable for the order of priority
Bus state controller
(BSC)
 The external address space is divided into six areas (CS0 to CS5) for management.
 The following features settable for each area independently.
Bus size (8, 16, or 32 bits): Available sizes depend on the area.
Number of access wait cycles (different wait cycles can be specified for read and write
access cycles in some areas)
Idle wait cycle insertion (between same area access cycles or different area access
cycles)
Specifying the memory to be connected to each area enables direct connection to
SRAM, SRAM with byte selection, SDRAM, and burst ROM (clocked synchronous or
asynchronous). The address/data multiplexed I/O (MPX) interface is also available.
 Outputs a chip select signal (CS0# to CS5#) according to the target area (CS assert or
negate timing can be selected by software)
 SDRAM refresh
Auto refresh or self-refresh mode selectable
 SDRAM burst access
Direct memory access
controller (DMAC)
 2 units (16 channels for unit 0, 16 channels for unit 1)
 Transfer modes: Single transfer mode and block transfer mode
 Transfer size
Unit 0: 1/2/4/16/32/64 bytes
Unit 1: 1/2/4/16 bytes
 Activation sources: Software trigger, external DMA requests (DREQ0 to DREQ2),
external interrupts, and interrupt requests from peripheral functions
General-purpose I/O
ports
 320-pin FBGA
I/O pins: 209
Input pins: 9
Pull-up/pull-down resistors: 209
Open-drain outputs: 9
5-V tolerance: 9
 176-pin HLQFP
I/O pins: 97
Input pins: 5
Pull-up/pull-down resistors: 97
Open-drain outputs: 5
5-V tolerance: 5
Event link controller (ELC)
Multi-function pin controller (MPC)
 87 event signals can be interlinked with the operation of modules.
 In particular, the operation of timer modules can be started by input event signals.
 Event-linked operation of signals of ports B and E is to be possible.
The locations of input/output functions are selectable from among multiple pins.
R01DS0228EJ0070 Rev.0.70
Dec 25, 2014
Page 3 of 52