RZT1_15 Datasheet, PDF (14/52 Pages) Renesas Technology Corp – 450 MHz/600MHz, MCU with ARM Cortex®-R4F

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RZ/T1 Group
1. Overview
Table 1.4
Pin Functions (2 / 7)
Classifications
Pin Name
Bus state controller (BSC) A0 to A25
D0 to D31
CS0# to CS5#
RD#
RD/WR#
BS#
AH#
WAIT#
WE0#
WE1#
WE2#
WE3#
DQMLL
DQMLU
DQMUL
DQMUU
RAS#
CAS#
CKE
Direct memory access
controller (DMAC)
DREQ0 to DREQ2
DACK0 to DACK2
Interrupt
TEND0 to TEND2
NMI
IRQ0 to IRQ15
ETH0_INT, ETH1_INT,
ETH2_INT
I/O
Output
I/O
Output
Output
Output
Output
Output
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Output
Output
Input
Input
Input
Description
Output the address.
Input and output the data.
Output the chip select signal for the external memory or device.
Outputs the strobe signal which indicates reading is in progress.
Outputs the strobe signal which indicates the read or write access.
Outputs the status signal which indicates the start of bus cycles.
Outputs the address hold signal for the device that uses the
multiplexed I/O bus.
Inputs the external wait control signal which inserts a wait cycle
into the bus cycles.
Outputs the write strobe signal to D7 to D0.
Outputs the write strobe signal to D15 to D8.
Outputs the write strobe signal to D23 to D16.
Outputs the write strobe signal to D31 to D24.
Outputs the data mask enable signal to D7 to D0 when SDRAM is
connected.
Outputs the data mask enable signal to D15 to D8 when SDRAM
is connected.
Outputs the data mask enable signal to D23 to D16 when SDRAM
is connected.
Outputs the data mask enable signal to D31 to D24 when SDRAM
is connected.
Outputs the low-address strobe signal to the SDRAM. This pin
should be connected to the RAS pin on the SDRAM.
Outputs the column-address strobe signal to the SDRAM. This pin
should be connected to the CAS pin on the SDRAM.
Outputs the clock enable signal to the SDRAM. This pin should be
connected to the CKE pin on the SDRAM.
Input the DMA transfer request signal from the external device.
Output the acknowledge signal which indicates acceptance of the
DMA transfer request from the external device.
Output the DMA transfer end signal.
Inputs the non-maskable interrupt request signal.
Input the external interrupt request signal.
Input the Ethernet PHY interrupt request signal.
R01DS0228EJ0070 Rev.0.70
Dec 25, 2014
Page 14 of 52