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RZT1_15 Datasheet, PDF (12/52 Pages) Renesas Technology Corp – 450 MHz/600MHz, MCU with ARM Cortex®-R4F
Under development Preliminary document
Specifications in this document are tentative and subject to change.
RZ/T1 Group
1.3 Block Diagram
Figure 1.1 shows a block diagram of a 320-pin device.
1. Overview
MTU3a × 9 channels
GPTA × 4 channels
SCIFA × 5 channels
RSPIa × 4 channels
ECATC *1
ETHERC × 3 ports
On-chip
extended
SRAM with
ECC
Cortex-M3*1
NVIC
MPU
USB
× 1 port
Cortex-R4F
VIC
MPU
TCM
Clock
generation
circuit
DMAC ×
16 channels
(unit 0)
DMAC ×
16 channels
(unit 1)
ELC
TPUa × 6 channels (unit 0)
TPUa × 6 channels (unit 1)
POE3
PPG (unit 0)
PPG (unit 1)
CMT × 2 channels (unit 0)
CMT × 2 channels (unit 1)
CMT × 2 channels (unit 2)
CMTW × 1 channel (unit 0)
CMTW × 1 channel (unit 1)
WDTA×1ch
Products incorporating an R-IN engine: WDTA×2ch
IWDTa
RIIC × 2 channels
RSCAN × 2 channels
SSI
DSMIF × 4 channels
CRC
CLMA
DOC
ECM
12-bit A/D converter × 8 channels (unit 0)
12-bit A/D converter × 16 channels (unit 1)
Temperature sensor
SPIBSC
BSC
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port B
Port C
Port D
Port E
Port F
Port G
Port H
Port J
Port K
Port L
Port M
Port N
Port P
Port R
Port S
Port T
Port U
ETHERC:
ECATC:
DMAC:
BSC:
SPIBSC:
WDTA:
IWDTa:
SCIFA:
RSPIa:
USB:
VIC:
NVIC:
MPU:
ELC:
TPUa:
MTU3a:
Ethernet controller
EtherCAT slave contoller
DMA controller
Bus state controller
SPI multi I/O bus controller
Watchdog timer
Independent watchdog timer
Serial communication interface with FIFO
Serial peripheral interface
USB 2.0 HS host/function module
Vector interrupt controller
Nested-type vector interrupt controller
Memory protection unit
Event link controller
16-bit timer pulse unit
Multi-function timer pulse unit 3
POE3:
GPTa:
PPG:
CMT:
CMTW:
RIICa:
RSCAN:
SSI:
DSMIF:
CRC:
CLMA:
DOC:
ECM:
Port output enable 3
General-purpose PWM timer
Programmable pulse generator
Compare match timer
Compare match timer W
I2C bus interface
CAN module
Serial sound interface
∆Σ interface
CRC (cyclic redundancy check) calculator
Clock monitor circuit
Data operation circuit
Error control module
Note 1. Only included in products incorporating an R-IN
engine
Figure 1.1
Block Diagram
R01DS0228EJ0070 Rev.0.70
Dec 25, 2014
Page 12 of 52