RZT1_15 Datasheet, PDF (22/52 Pages) Renesas Technology Corp – 450 MHz/600MHz, MCU with ARM Cortex®-R4F

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RZ/T1 Group
1. Overview
Table 1.5
Pin Number
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C1
C2
C3
C4
Pin Assignments (320-Pin FBGA) (1 / 8)
Pin Name
VSS
PC2 / ETH0_TXC / ETH1_RXD2 / CATI2CDATA / SDA0
PJ3 / IRQ11 / ETH0_TXD0 / ADTRG0
PJ1 / ETH0_TXD2 / CATLEDSTER / RSPCK3
PF7 / IRQ7 / A25 / ETH0_TXER / RTS3# / SSL30
PB4 / A24 / ETH1_COL / ETH0_RXER / CATSYNC0 / CATLATCH0 / RXD3 / MOSI3_BLUE / MDAT0
PB0 / ETH1_RXDV / MTCLKB / TCLKD / TIC3
PC0 / WAIT# / ETH1_RXD2 / GTETRG / SCL1 / MDAT3
PF6 / ETH1_RXD0 / MTIOC3D / GTIOC0B / TOC2
VCCQ33
P54 / CLKOUT25M1 / MOSI2_RED
VSS
AN007
AN005
AN002
AVCC0
AVCC1
VREFH1
P17 / CS5# / ETH1_TXER / PHYRESETOUT# / ADTRG0
VSS
PJ5 / ETH0_RXD1 / TIOCD0 / RXD3
PJ4 / ETH0_RXD0 / TXD3
PC3 / ETH0_RXC / ETH0_RXDV / CATI2CCLK / RXD4 / SCL0 / CRXD1
PJ2 / IRQ10 / ETH0_TXD1 / MISO3
PJ0 / IRQ8 / ETH0_TXD3 / CATLEDERR / MOSI3_RED
PB5 / ETH_MDIO / TCLKB / POE0# / POE10# / CTS3# / RSPCK3
PB2 / ETH1_RXC / ETH0_RXD1 / CATSYNC1 / CATLATCH1 / MTIOC1A / SSL30 / MDAT1
PC1 / IRQ9 / ETH1_RXD3 / PHYLINK0 / SDA1 / MDAT2
PB7 / ETH1_RXD1 / MTIOC3B / GTIOC0A / TOC3
P86 / AN1_ANEX0 / ETH1_TXD0 / MTIOC4B / GTIOC2A / TOC1 / RSPCK2
PD7 / AN115 / ETH1_TXD1 / MTIOC4D / GTIOC2B / TOC0
P52 / ETH0_INT / SSL20
AN006
AN003
AN001
AVSS0
AVSS1
VREFL1
P16 / CS4# / CS2# / MTIOC3B / GTIOC0A
P15 / CS3# / CKE / MTIOC3D / GTIOC0B
PJ7 / IRQ15 / ETH0_RXD3 / CATLEDRUN / CTS3#
PJ6 / IRQ14 / ETH0_RXD2 / CATIRQ / SCK3
PU2 / IRQ2 / ETH2_CRS / TIOCD9 / RXD3
PL7 / IRQ15 / ETH2_RXDV
R01DS0228EJ0070 Rev.0.70
Dec 25, 2014
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