AN91267 Datasheet, PDF (50/62 Pages) Ramtron International Corporation – Getting Started with PSoC

Getting Started with PSoC® 4 BLE
Power Supply and Monitoring
PSoC 4 BLE is capable of operating from a single 1.9-V to 5.5-V supply. There are multiple internal regulators to support the
different device power modes. PSoC 4 BLE has three types of voltage-monitoring capabilities: POR, BOD, and LVD.
Clocking System
PSoC 4 BLE has the following clock sources:
 Internal main oscillator (IMO): The IMO is the primary source of internal clocking in PSoC 4 BLE. The CPU and all high-
speed peripherals can operate from the IMO or an external crystal oscillator (ECO). PSoC 4 BLE has multiple peripheral
clock dividers operating from either the IMO or the ECO, which generate clocks for high-speed peripherals. The IMO can
generate clocks in the range of 3 MHz to 48 MHz in 1-MHz increments with an accuracy of ±2 percent.
 Internal low-speed oscillator (ILO): The ILO is a very-low-power 32-kHz oscillator, which primarily generates clocks for
low-speed peripherals operating in Deep-Sleep mode except the BLESS (see WCO).
 External crystal oscillator (ECO): The external crystal oscillator with a built-in tunable crystal load capacitance is used to
generate a highly accurate 24-MHz clock. It is primarily used to clock the BLE subsystem that generates the RF clocks.
The high-accuracy ECO clock can also be used as a clock source for the PSoC 4 BLE device’s high-frequency clock
(HFCLK).
 Watch crystal oscillator (WCO): The 32-kHz WCO is used as one of the sources for LFCLK (along with ILO). WCO is
used to accurately maintain the time interval for BLE advertising and connection events. Similar to ILO, WCO is also
available in all modes except the Hibernate and Stop modes.
Figure 60 shows the clocking architecture of a PSoC 4 BLE device.
Figure 60. PSoC 4 BLE Clocking System
32.768 KHz external clock
WCO
ILO
ECO
IMO
EXTCLK
Low frequency clock to WDT, BLE low power logic,
LCD, CPU timer and UDB
Prescaler
/2ⁿ (n=0..2)
To BLE Link Layer
Divider
/2ⁿ (n=0..3)
Prescaler
/2ⁿ (n=0..7)
To Flash and peripherals that
need specific divided clock
To CPU & bus interface
of peripherals
LFCLK
LLCLK
HFCLK
SYSCLK
Clock enables to SCB, CSD, TCPWM,
Divider 0
/2ⁿ (n=0..16)
LCD, PASS & UDB to divide HFCLK
0-9
Divider 9
/2ⁿ (n=0..16)
Fractional Divider0
/( 2^m+(2ⁿ-1)/2ⁿ )
(m=0..16, n=0..5)
Fractional Divider1
/( 2^m+(2ⁿ-1)/2ⁿ )
(m=0..16, n=0..5)
PER0_CLK
PER15_CLK
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Document No. 001-91267 Rev. *D
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