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AN91267 Datasheet, PDF (5/62 Pages) Ramtron International Corporation – Getting Started with PSoC
Getting Started with PSoC® 4 BLE
PSoC 4 BLE Features
The PSoC 4 BLE product family is based on Cypress’s PSoC 4100/4200 family of devices. PSoC 4 BLE features include a
CPU and memory subsystem, a BLE subsystem, a digital subsystem, an analog subsystem, and system resources, as Figure
4 shows. Figure 4 shows the features available in the CY8C4247-BL family of devices. Subsets of these features are available
in other device families; see Table 2.
If you are familiar with the PSoC 4100/4200 family of devices, PSoC 4 BLE supports all the features supported by
PSoC 4100/4200 and adds the following:
 BLE radio with link-layer hardware
 External crystal oscillator and watch crystal oscillator
 Four opamps (compared to two in the PSoC 4100/4200 family) that are active in device low-power (Deep-Sleep) mode
 128 KB/256 KB of flash and 16 KB/32 KB of SRAM (compared to 32 KB of flash and 4 KB of SRAM in PSoC 4100/4200
family)
See Appendix D: PSoC 4 BLE Device for a brief description of the features. For in-depth information, see the PSoC 4 BLE
family datasheet, TRM, and application notes.
Figure 4. PSoC 4 BLE Architecture (CY8C4248-BL)
PSoC 4 BLE
Architecture
32-bit
AHB-Lite
System Resources
Power
Sleep Control
WIC
POR LVD
REF BOD
PWRSYS
NVLatches
Boost
Clock
Clock Control
WDT
IMO ILO
Reset
Reset Control
XRES
CPU & Memory
SWD/TC
Cortex
M0
48 MHz
FAST MUL
NVIC, IRQMX
SPCIF
FLASH
256 KB
Read Accelerator
SRAM
32 KB
SRAM Controller
ROM
8 KB
ROM Controller
Peripherals
PERI
System Interconnect (Single Layer AHB)
Peripheral Interconnect (MMIO)
Programmable
Analog
x1
SAR
(12-bit)
SMX
CTBm
2x OpAmp x2
Programmable
Digital
UDB
UDB
x4
UDB
UDB
Port Interface & Digital System Interconnect (DSI)
Bluetooth Low
Energy Subsystem
BLE Baseband
Peripheral
1KB SRAM
GFSK Modem
2.4 GHz
GFSK
Radio
Active/Sleep
Deep Sleep
Hibernate
IO Subsystem
High Speed I/O Matrix
36x GPIOs
IO: Antenna/Power/Crystal
www.cypress.com
Document No. 001-91267 Rev. *D
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