AN91267 Datasheet, PDF (39/62 Pages) Ramtron International Corporation – Getting Started with PSoC

Getting Started with PSoC® 4 BLE
Appendix A: BLE Device Family Comparison
Table 2 summarizes the features and capabilities of the BLE device family from Cypress.
Table 2. BLE Device Families
Features
BLE Subsystem
CPU
Flash Memory
SRAM
GPIOs
CapSense
CapSense
Gestures
ADC
Opamps
Comparators
Current DACs
Power Supply
Range
Low-Power
Modes
Segment LCD
Drive
Serial
Communication
CY8C41x7-BL
BLE radio and link-
layer hardware
blocks with
Bluetooth 4.1-
compatible protocol
stack
24-MHz ARM
Cortex-M0 CPU with
single-cycle multiply
128 KB
16 KB
Up to 36
Up to 35 sensors
On selected devices
CY8C42x7-BL
BLE radio and link-
layer hardware blocks
with Bluetooth 4.1-
compatible protocol
stack
48-MHz ARM Cortex-
M0 CPU with single-
cycle multiply
128 KB
16 KB
Up to 36
Up to 35 sensors
On selected devices
Device Family
CYBL10X6X
BLE radio and link-
layer hardware blocks
with Bluetooth 4.1-
compatible protocol
stack
48-MHz ARM Cortex-
M0 CPU with single-
cycle multiply
128 KB
16 KB
Up to 36
Up to 35 sensors
On selected devices
CY8C41x8-BL
BLE radio and link-
layer hardware
blocks with
Bluetooth 4.1-
compatible protocol
stack
24-MHz ARM
Cortex-M0 CPU with
single-cycle multiply
256 KB
32 KB
Up to 36
Up to 35 sensors
On selected devices
CY8C42x8-BL
BLE radio and link-
layer hardware blocks
with Bluetooth 4.1-
compatible protocol
stack
48-MHz ARM Cortex-
M0 CPU with single-
cycle multiply
256 KB
32 KB
Up to 36
Up to 35 sensors
On selected devices
12-bit, 806-ksps
SAR ADC with
sequencer
12-bit, 1-Msps SAR
ADC with sequencer
2 programmable
opamps that are
active in Deep-Sleep
mode
4 programmable
opamps that are active
in Deep-Sleep mode
2 low-power
2 low-power
comparators with the comparators with the
wakeup feature
wakeup feature
One 7-bit, and one
8-bit
One 7-bit, and one 8-
bit
1.9 V to 5.5 V
1.9 V to 5.5 V
12-bit, 1-Msps SAR
ADC with sequencer
None
None
None
1.9 V to 5.5 V
12-bit, 806-ksps
SAR ADC with
sequencer
12-bit, 1-Msps SAR
ADC with sequencer
2 programmable
opamps that are
active in Deep-Sleep
mode
4 programmable
opamps that are
active in Deep-Sleep
mode
2 low-power
2 low-power
comparators with the comparators with the
wakeup feature
wakeup feature
One 7-bit, and one
8-bit
One 7-bit, and one 8-
bit
1.9 V to 5.5 V
1.9 V to 5.5 V
Deep-Sleep mode at
1.3 µA
Hibernate mode at
150 nA
Stop mode at 60 nA
4-COM, 32-segment
LCD drive on select
devices
2 independent serial
communication
blocks (SCBs) with
programmable I²C,
SPI, or UART
Deep-Sleep mode at
1.3 µA
Hibernate mode at
150 nA
Stop mode at 60 nA
4-COM, 32-segment
LCD drive on select
devices
2 independent SCBs
with programmable I²C,
SPI, or UART
Deep-Sleep mode at
1.3 µA
Hibernate mode at
150 nA
Stop mode at 60 nA
4-COM, 32-segment
LCD drive on select
devices
1 or 2 independent
SCBs with
programmable I²C,
SPI, or UART
Deep-Sleep mode at
1.3 µA
Hibernate mode at
150 nA
Stop mode at 60 nA
4-COM, 32-segment
LCD drive on select
devices
2 independent serial
communication
blocks (SCBs) with
programmable I²C,
SPI, or UART
Deep-Sleep mode at
1.3 µA
Hibernate mode at
150 nA
Stop mode at 60 nA
4-COM, 32-segment
LCD drive on select
devices
2 independent SCBs
with programmable
I²C, SPI, or UART
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Document No. 001-91267 Rev. *D
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