AN91267 Datasheet, PDF (46/62 Pages) Ramtron International Corporation – Getting Started with PSoC

Getting Started with PSoC® 4 BLE
ARM Cortex-M0 and Memory
PSoC 4 BLE has a 32-bit ARM Cortex-M0 CPU, capable of operating at a maximum frequency of 48 MHz, providing a 43-
DMIPS performance. The CPU supports single-cycle 32-bit multiplication. PSoC 4 BLE has 16 KB/32 KB of SRAM and
128 KB/256 of flash memory that can service most of the BLE application use; the flash includes a read accelerator. The
device also provides 512 bytes of supervisory flash area for you to store user-specific data such as BLE device address and
encryption keys.
Programmable Digital Peripherals
PSoC 4 BLE provides a rich set of digital peripherals including programmable serial communication blocks (SCBs),
timer counter pulse width modulators (TCPWMs), and programmable logic arrays called universal digital blocks (UDBs).
Programmable SCBs
PSoC 4 BLE has independent run-time programmable SCBs with I²C, SPI, or UART. The SCB supports the following features:
 ^{Standard SPI master and slave functionality with Motorola®, Texas Instruments®, and National Semiconductor® protocols}
 ^{Standard UART functionality with smart-card reader, Local Interconnect Network (LIN), and Infrared Data Association}
(IrDA) protocols
 ^{Standard I2C master and slave functionality}
 ^{SPI and EZI2C mode, which allows operation without CPU intervention}
 ^{Low-power (Deep-Sleep) mode of operation for SPI and I2C protocols (using an external clock)}
For more information, refer to the PSoC 4 SCB Component datasheet.
Programmable TCPWMs
PSoC 4 BLE has four programmable 16-bit TCPWM blocks. Each TCPWM can implement a 16-bit timer, counter, PWM, or
quadrature decoder. TCPWMs provide complementary outputs and selectable start, reload, stop, count, and capture event
signals. The PWM mode supports center-aligned, edge, and pseudo random operations.
For more information, refer to the PSoC 4 TCPWM Component datasheet.
Universal Digital Blocks
UDBs are programmable logic blocks that provide functionalities similar to CPLD and FPGA blocks, as Figure 59 shows.
UDBs allow you to create a variety of digital functions such as timer, counter, PWM, pseudo random sequence (PRS), CRC,
shift register, SPI, UART, I2S, and custom combinational and sequential logic circuits.
Each UDB has two programmable logic devices (PLDs), each with 12 inputs and 8 product terms. PLDs can form registered or
combinational sum-of-products logic. Additionally, an 8-bit single-cycle arithmetic logic unit (ALU), known as a “datapath,” is
present in each UDB. The datapath helps with the efficient implementation of functions such as timer, counter, PWM, and
CRC.
UDBs also provide a switched digital signal interconnect (DSI) fabric that allows signals from peripherals and ports to be
routed to and through the UDBs for communication and control.
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Document No. 001-91267 Rev. *D
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