HYB18T512161BF Datasheet, PDF(8/41 Page) Qimonda AG – 512-Mbit x16 DDR2 SDRAM

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HYB18T512161BF Datasheet, PDF (8/41 Pages) Qimonda AG – 512-Mbit x16 DDR2 SDRAM

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Internet Data Sheet

HYB18T512161BFâ20/22/25/28/33

512-Mbit Double-Data-Rate-Two SDRAM

Abbreviation

SSTL

LV-CMOS

CMOS

OD

TABLE 4

Abbreviations for Buffer Type

Description

Serial Stub Terminated Logic (SSTL_18)

Low Voltage CMOS

CMOS Levels

Open Drain. The corresponding pin has 2 operational states, active low and tristate, and

allows multiple devices to share as a wire-OR.

FIGURE 1

Pin Configuration for Ã16 components, P-TFBGA-84 (top view)

6''

.#

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666

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03 37

Note:

1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is

data strobe for DQ[7:0]

2. LDM is the data mask signal for DQ[7:0], UDM is the data

mask signal for DQ[15:8]

3. VDDL and VDDSL are power and ground for the DLL. They

are isolated on the device from VDD, VDDQ, VSS and VSSQ.

Rev. 1.43, 2006-11

8

03292006-L40N-L04G

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