HYB18T512161BF Datasheet, PDF (27/41 Pages) Qimonda AG – 512-Mbit x16 DDR2 SDRAM

Internet Data Sheet
HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
5.7.2
AC Timing Parameters
List of Timing Parameters
Parameter
Symbol
DQ output access time from CK / t_AC
CK
CAS A to CAS B command period t_CCD
CK, CK high-level width
t_CH
CKE minimum high and low pulse t_CKE
width
CK, CK low-level width
t_CL
Auto-Precharge write recovery + t_DAL
precharge time
Minimum time clocks remain ON
after CKE asynchronously drops
LOW
t_DELAY
DQ and DM input hold time
t_DH
(differential data strobe)
DQ and DM input hold time (single t_DH1
ended data strobe)
DQ and DM input pulse width (each t_DIPW
input)
DQS output access time from CK / t_DQSCK
CK
DQS input low (high) pulse width t_DQSL,H
(write cycle)
DQS-DQ skew (for DQS &
associated DQ signals)
t_DQSQ
Write command to 1st DQS latching t_DQSS
transition
DQ and DM input setup time
t_DS
(differential data strobe)
DQ and DM input setup time (single t_DS1
ended data strobe)
DQS falling edge hold time from CK t_DSH
(write cycle)
DQS falling edge to CK setup time t_DSS
(write cycle)
Clock half period
t_HP
Data-out high-impedance time from t_HZ
CK / CK
–20
Min.
–450
–22
Max. Min.
+450 –450
TABLE 29
Timing Parameter by Speed Grade
Max.
–25
Min.
Max.
Unit Note¹⁾
2)3)4)5)6)
+450 –500
+500 ps
2
—
2
—
0.45
0.55 0.45
0.55
3
—
3
—
0.45
0.55
WR + t_RP —
0.45
0.55
WR + t_RP —
t_IS + t_CK + ––
t_IH
t_IS + t_CK + ––
t_IH
145
–– 220
––
-105
–– -30
––
2
—
0.45
0.55
3
—
0.45
0.55
WR + t_RP —
t_IS + t_CK + ––
t_IH
250
––
0
––
t_CK
t_CK
t_CK
t_CK
t_CK
7)18)
ns ⁸⁾
ps ⁹⁾
ps ⁹⁾
0.35
–450
—
0.35
+450 –450
—
0.35
+450 –500
—
+500
t_CK
ps ⁹⁾
0.35
—
—
0.35
450 —
—
0.35
450
—
—
t_CK
450
ps
10)
WL –
0.25
20
-105
WL +
0.25
—
WL –
0.25
95
—
-30
WL +
0.25
––
WL –
0.25
125
––
0
WL +
0.25
––
t_CK
ps ⁹⁾
––
ps ⁹⁾
0.2
—
0.2
—
0.2
—
t_CK
0.2
—
0.2
—
0.2
—
t_CK
MIN. (t_CL, t_CH)
MIN. (t_CL, t_CH)
MIN. (t_CL, t_CH)
—
11)
—
t_AC.MAX —
t_AC.MAX —
t_AC.MAX ps
12)
Rev. 1.43, 2006-11
27
03292006-L40N-L04G