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HYB18T512161BF Datasheet, PDF (28/41 Pages) Qimonda AG – 512-Mbit x16 DDR2 SDRAM
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Internet Data Sheet
HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
Address and control input hold time tIH
Address and control input pulse tIPW
width
(each input)
Address and control input setup tIS
time
DQ low-impedance time from CK / tLZ(DQ)
CK
DQS low-impedance from CK / CK tLZ(DQS)
Mode register set command cycle tMRD
time
OCD drive mode output delay
tOIT
Data output hold time from DQS tQH
Data hold skew factor
tQHS
Average periodic refresh Interval tREFI
Auto-Refresh to Active/Auto-
tRFC
Refresh command period
Read preamble
Read postamble
Active bank A to Active bank B
command period
tRPRE
tRPST
tRRD
Internal Read to Precharge
tRTP
command delay
Write preamble
Write postamble
Write recovery time for write without
Auto-Precharge
tWPRE
tWPST
tWR
Write recovery time for write with WR
Auto-Precharge
Internal Write to Read command tWTR
delay
Exit power down to any valid
command
(other than NOP or Deselect)
tXARD
Exit active power-down mode to
Read command (slow exit, lower
power)
tXARDS
Exit precharge power-down to any tXP
valid command (other than NOP or
Deselect)
–20
Min.
525
0.6
–22
Max.
—
Min.
525
0.6
Max.
—
—
400
—
400
—
2×
tAC.MIN
tAC.MIN
2
tAC.MAX 2 ×
tAC.MIN
tAC.MAX tAC.MIN
—
2
tAC.MAX
tAC.MAX
—
0
12
tHP–tQHS —
—
600
—
7.8
—
3.9
105
—
0
12
tHP–tQHS —
—
600
—
7.8
—
3.9
105
—
0.9
1.1 0.9
1.1
0.40
0.60 0.40
0.60
10
—
10
—
7.5
—
7.5
—
0.35 x tCK —
0.40
0.60
13
—
0.35 x tCK —
0.40
0.60
13
—
tWR/tCK —
7.5
—
tWR/tCK —
7.5
—
2
—
2
—
10 – AL —
9 – AL —
2
—
2
—
–25
Min.
575
0.6
Max.
—
—
450
—
2×
tAC.MIN
tAC.MIN
2
tAC.MAX
tAC.MAX
—
0
12
tHP–tQHS —
—
600
—
7.8
—
3.9
105
—
0.9
1.1
0.40
0.60
10
—
7.5
—
0.35 x tCK —
0.40
0.60
15
—
tWR/tCK —
7.5
—
2
—
8 – AL —
2
—
Unit Note1)
2)3)4)5)6)
ps
tCK
ps
ps
12)
ps
12)
tCK
ns
—
ps
µs
13)14)
µs
13)15)
ns
16)
tCK
12)
tCK
12)
ns
14)17)
ns
tCK
tCK
17)
ns
tCK
18)
ns
19)
tCK
20)
tCK
20)
tCK
Rev. 1.43, 2006-11
28
03292006-L40N-L04G
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