HYB18T512161BF Datasheet, PDF (26/41 Pages) Qimonda AG – 512-Mbit x16 DDR2 SDRAM

Internet Data Sheet
5.7
AC Characteristics
HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
5.7.1
Speed Grade Definitions
Speed Grade
TABLE 28
Speed Grade Definition
–20
–22
–25
–28
–33
Unit Note
Parameter
Symbol Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Clock
Frequency
@ CL = 3 t_CK
@ CL = 4 t_CK
@ CL = 5 t_CK
@ CL = 6 t_CK
@ CL = 7 t_CK
Row Active Time
t_RAS
3.75 8
3.75 8
3.75 8
3.75 8
3.75 8
ns
3.75 8
3.75 8
3.75 8
3.75 8
3.75 8
ns
38
38
38
38
3.33 8
ns
2.5 8
2.5 8
2.5 8
2.8 8
3.33 8
ns
2.0 8
2.2 8
— — — — — — ns
45 70k 45 70k 45 70k 45 70k 45 70k ns
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)
5)
Row Cycle Time
t_RC
60 —
60 —
60 —
60 —
60 —
ns
1)2)3)4)
RAS-CAS-Delay
t_RCD
15 —
15 —
15 —
15 —
15 —
ns
1)2)3)4)
Row Precharge Time
t_RP
15 —
15 —
15 —
15 —
15 —
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other Slew Rates see Chapter 7.Timings
are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0).
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, input reference
level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until V_REF stabilizes. During the period before V_REF stabilizes, CKE = 0.2 x V_DDQ is recognized as low.
4) The output timing reference voltage level is V_TT.
5) t_RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI.
Rev. 1.43, 2006-11
26
03292006-L40N-L04G