HYB18T512161BF Datasheet, PDF (11/41 Pages) Qimonda AG – 512-Mbit x16 DDR2 SDRAM

Internet Data Sheet
HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
Field Bits Type¹⁾
Description
BT
3
w
BL
[2:0] w
Burst Type
0_B BT Sequential
1_B BT Interleaved
Burst Length
Note: All other bit combinations are illegal.
010_B BL 4
011_B BL 8
1) w = write only register bits
2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing t_WR (in ns) by t_CK (in ns) and
rounding up to the next integer: WR [cycles] ≥ t_WR (ns) / t_CK (ns). The mode register must be programmed to fulfill the minimum requirement
for the analogue t_WR timing WR_MIN is determined by t_CK.MAX and WR_MAX is determined by t_CK.MIN.
Rev. 1.43, 2006-11
11
03292006-L40N-L04G