HYB18T512161BF Datasheet, PDF (21/41 Pages) Qimonda AG – 512-Mbit x16 DDR2 SDRAM

Internet Data Sheet
HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
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Single-ended AC Input Test Conditions Diagram
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TABLE 22
Differential DC and AC Input and Output Logic Levels
Symbol Parameter
Min.
Max.
Unit Note
V_IN(dc)
DC input signal voltage
–0.3
V_DDQ + 0.3
—
1)
V_ID(dc)
DC differential input voltage
0.25
V_DDQ + 0.6
—
2)
V_ID(ac)
AC differential input voltage
0.5
V_DDQ + 0.6
V
3)
V_IX(ac)
AC differential cross point input voltage 0.5 × V_DDQ – 0.175
0.5 × V_DDQ + 0.175
V
4)
V_OX(ac)
AC differential cross point output voltage 0.5 × V_DDQ – 0.125
0.5 × V_DDQ + 0.125
V
5)
1) V_IN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc.
2) V_ID(dc) specifies the input differential voltage V_TR– V_CP required for switching. The minimum value is equal to V_IH(dc) – V_IL(dc).
3) V_ID(ac) specifies the input differential voltage V_TR – V_CP required for switching. The minimum value is equal to V_IH(ac) – V_IL(ac).
4) The value of V_IX(ac) is expected to equal 0.5 × V_DDQ of the transmitting device and V_IX(ac) is expected to track variations in V_DDQ. V_IX(ac)
indicates the voltage at which differential input signals must cross.
5) The value of V_OX(ac) is expected to equal 0.5 × V_DDQ of the transmitting device and V_OX(ac) is expected to track variations in V_DDQ. V_OX(ac)
indicates the voltage at which differential input signals must cross.
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FIGURE 3
Differential DC and AC Input and Output Logic Levels Diagram
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9664
Rev. 1.43, 2006-11
21
03292006-L40N-L04G