HYB18T512161BF Datasheet, PDF (31/41 Pages) Qimonda AG – 512-Mbit x16 DDR2 SDRAM

Internet Data Sheet
HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol –28
Min.
Max.
–33
Min.
Max.
Unit Note¹⁾
2)3)4)5)6)
Auto-Refresh to Active/Auto-Refresh command t_RFC
period
Read preamble
t_RPRE
Read postamble
t_RPST
Active bank A to Active bank B command period t_RRD
Internal Read to Precharge command delay
t_RTP
Write preamble
t_WPRE
Write postamble
t_WPST
Write recovery time for write without Auto-
t_WR
Precharge
Write recovery time for write with Auto-Precharge WR
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
t_WTR
t_XARD
Exit active power-down mode to Read command t_XARDS
(slow exit, lower power)
105
—
0.9
1.1
0.40
0.60
10
—
7.5
—
0.35 x t_CK —
0.40
0.60
15
—
t_WR/t_CK
—
7.5
—
2
—
7 – AL —
105
—
0.9
1.1
0.40
0.60
10
—
7.5
—
0.35 x t_CK —
0.40
0.60
15
—
t_WR/t_CK
—
7.5
—
2
—
6 – AL —
ns
16)
t_CK
12)
t_CK
12)
ns
14)17)
ns
t_CK
t_CK
17)
ns
t_CK
18)
ns
19)
t_CK
20)
t_CK
20)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
t_XP
2
—
2
—
t_CK
Exit Self-Refresh to non-Read command
t_XSNR
t_RFC +10 —
t_RFC +10 —
ns
Exit Self-Refresh to Read command
t_XSRD
200
—
200
—
t_CK
1) V_DDQ, V_DD refer to Chapter 1.
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other Slew Rates see Chapter 5 of this
data sheet.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross.The DQS / DQS input reference
level is the crosspoint when in differential strobe mode;The input reference level for signals other than CK/CK, DQS / DQS is defined in
Chapter 5.3 of this data sheet.
5) Inputs are not recognized as valid until V_REF stabilizes. During the period before V_REF stabilizes, CKE = 0.2 x V_DDQ is recognized as low.
6) The output timing reference voltage level is V_TT. See Chapter 5 for the reference load for timing measurements.
7) For each of the terms, if not already an integer, round to the next highest integer. t_CK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock frequency change
during power-down, a specific procedure is required.
9) timing is referenced to Industrial standard definition
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
11) MIN (t_CL, t_CH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for t_CL and t_CH).
12) The t_HZ, t_RPST and t_LZ, t_RPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(t_HZ, t_RPST), or begins driving (t_LZ, t_RPRE). t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
13) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
14) 0 °C ≤ T_CASE ≤ 85 °C
15) 85 °C < T_CASE ≤ 95 °C
16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
Rev. 1.43, 2006-11
31
03292006-L40N-L04G