HYB18T512161BF Datasheet, PDF (13/41 Pages) Qimonda AG – 512-Mbit x16 DDR2 SDRAM

Internet Data Sheet
HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
%$
%$


$
$ $ $ $ $ $ $ $ $ $ $ $

65)

3$65
UHJDGGU
Field Bits
Type¹⁾
TABLE 8
EMRS(2) Programming Extended Mode register Definition (BA[1:0]=10_B)
Description
BA [14:13] w
A
[12:8] w
A
7
w
Bank Adress[14:13]
00_B BA MRS
01_B BA EMRS(1)
10_B BA EMRS(2)
11_B BA EMRS(3): Reserved
Address Bus[12:8]
0_B A[12:8] Address bits
Address Bus[7]
Note: adapted self refresh rate for Tcase > 85°C
0_B A7 disable
1_B A7 enable ²⁾³⁾
A
[6:3] w
Address Bus[6:3]
0_B A[6:3] Address bits
Partial Self Refresh for 4 banks
A
[2:0] w
Address Bus[2:0], Partial Array Self Refresh for 4 Banks
000_B PASR0 Full Array
001_B PASR1 Half Array (BA[1:0]=00, 01)
010_B PASR2 Quarter Array (BA[1:0]=00)
011_B PASR3 Not defined
100_B PASR4 3/4 array (BA[1:0]=01, 10, 11)
101_B PASR5 Half array (BA[1:0]=10, 11)
110_B PASR6 Quarter array (BA[1:0]=11)
111_B PASR7 Not defined
1) w = write only
2) When DRAM is operated at 85C ≤ T_Case ≤ 95C the extended self refresh rate must be enabled by setting bit A7 to "1" before the self refresh
mode can be entered.
3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refresh
is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued
Rev. 1.43, 2006-11
13
03292006-L40N-L04G