HYB18T512161BF Datasheet, PDF (5/41 Pages) Qimonda AG – 512-Mbit x16 DDR2 SDRAM

Internet Data Sheet
HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
2
Pin Configuration
2.1
Pin Configuration
The pin configuration of a DDR2 SDRAM is listed by function in Table 2. The abbreviations used in the Pin#/Buffer Type
columns are explained in Table 3 and Table 4 respectively. The pin numbering for the FBGA package is depicted in Figure 1
for ×16.
Ball#/Pin#
Name
Pin
Type
Clock Signals ×16 organization
J8
CK
I
K8
CK
I
K2
CKE
I
Control Signals ×16 organization
K7
RAS
I
L7
CAS
I
K3
WE
I
L8
CS
I
Address Signals ×16 organization
L2
BA0
I
L3
BA1
I
L1
NC
–
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
–
Function
TABLE 2
Pin Configuration of DDR SDRAM
Clock Signal CK, Complementary Clock Signal CK
Clock Enable
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
Chip Select
Bank Address Bus 1:0
Rev. 1.43, 2006-11
5
03292006-L40N-L04G