HYB18T512161BF Datasheet, PDF (30/41 Pages) Qimonda AG – 512-Mbit x16 DDR2 SDRAM

Internet Data Sheet
HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol –28
Min.
Max.
TABLE 30
Timing Parameter by Speed Grade
–33
Min.
Max.
Unit Note¹⁾
2)3)4)5)6)
DQ output access time from CK / CK
t_AC
CAS A to CAS B command period
t_CCD
CK, CK high-level width
t_CH
CKE minimum high and low pulse width
t_CKE
CK, CK low-level width
t_CL
Auto-Precharge write recovery + precharge time t_DAL
Minimum time clocks remain ON after CKE
asynchronously drops LOW
t_DELAY
DQ and DM input hold time (differential data
t_DH
strobe)
DQ and DM input hold time (single ended data t_DH1
strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ
signals)
t_DIPW
t_DQSCK
t_DQSL,H
t_DQSQ
Write command to 1st DQS latching transition
DQ and DM input setup time (differential data
strobe)
t_DQSS
t_DS
DQ and DM input setup time (single ended data t_DS1
strobe)
DQS falling edge hold time from CK (write cycle) t_DSH
DQS falling edge to CK setup time (write cycle) t_DSS
Clock half period
t_HP
Data-out high-impedance time from CK / CK
t_HZ
Address and control input hold time
t_IH
Address and control input pulse width
t_IPW
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
t_IS
t_LZ(DQ)
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
t_LZ(DQS)
t_MRD
t_OIT
t_QH
t_QHS
t_REFI
–550
+550
–600
+600
ps
2
—
2
—
t_CK
0.45
0.55
0.45
0.55
t_CK
3
—
3
—
t_CK
0.45
0.55
0.45
0.55
t_CK
WR + t_RP —
WR + t_RP —
t_CK
t_IS + t_CK + ––
t_IS + t_CK + ––
ns
t_IH
t_IH
275
––
295
––
ps
25
––
45
––
ps
0.35
–550
0.35
—
—
+550
—
450
0.35
–600
0.35
—
—
t_CK
+600
ps
—
t_CK
450
ps
WL – 0.25 WL + 0.25 WL – 0.25 WL + 0.25 t_CK
150
––
170
––
ps
25
––
45
––
ps
0.2
—
0.2
—
t_CK
0.2
—
0.2
—
t_CK
MIN. (t_CL, t_CH)
MIN. (t_CL, t_CH)
—
—
t_AC.MAX
—
t_AC.MAX
ps
625
—
675
—
ps
0.6
—
0.6
—
t_CK
500
—
550
—
ps
2×
t_AC.MIN
t_AC.MIN
2
0
t_AC.MAX
t_AC.MAX
—
12
2×
t_AC.MIN
t_AC.MIN
2
0
t_AC.MAX
ps
t_AC.MAX
ps
—
t_CK
12
ns
t_HP–t_QHS —
t_HP–t_QHS —
—
—
600
—
600
ps
—
7.8
—
7.8
µs
—
3.9
—
3.9
µs
7)18)
8)
9)
9)
9)
10)
9)
9)
11)
12)
12)
12)
13)14)
13)15)
Rev. 1.43, 2006-11
30
03292006-L40N-L04G