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| HYB18T512161BF Datasheet, PDF (12/41 Pages) Qimonda AG – 512-Mbit x16 DDR2 SDRAM | |||
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Internet Data Sheet
HYB18T512161BFâ20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
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4RII
'462&'3URJUDP5WW $/ 5WW',&'//
UHJDGGU
Z Z Z Z ZZZ
Field
BA1
BA0
Qoff
Bits Type1)
14 reg. addr.
13
12 w
DQS 10
OCD [9:7]
Program
AL
[5:3]
RTT
2,6
DIC
1
DLL
0
1) w = write only register bits
TABLE 7
Extended Mode Register Definition (BA[1:0] = 01B)
Description
Bank Address [1]
0B BA1 Bank Address
Bank Address [0]
0B BA0 Bank Address
Output Disable
0B QOff Output buffers enabled
1B QOff Output buffers disabled
Complement Data Strobe (DQS Output)
0B DQS Enable
1B DQS Disable
Off-Chip Driver Calibration Program
000B OCD OCD calibration mode exit, maintain setting
001B OCD Drive (1)
010B OCD Drive (0)
100B OCD Adjust mode
111B OCD OCD calibration default
Additive Latency
Note: All other bit combinations are illegal.
000B AL 0
001B AL 1
010B AL 2
011B AL 3
100B AL 4
101B AL 5
110B AL 6
Nominal Termination Resistance of ODT
00B RTT â (ODT disabled)
01B RTT 75 Ohm
10B RTT 150 Ohm
11B RTT 50 Ohm
Off-chip Driver Impedance Control
0B DIC Full (Driver Size = 100%)
1B DIC Reduced
DLL Enable
0B DLL Enable
1B DLL Disable
Rev. 1.43, 2006-11
12
03292006-L40N-L04G
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