HYB18T1G400BF_07 Datasheet, PDF (63/74 Pages) Qimonda AG – 1-Gbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
Symbol Parameter
Min.
TABLE 58
Absolute Jitter Value Definitions
Max.
Unit
t_CK.ABS Clock period
t t _CK.AVG(Min) + _JIT.PER(Min)
t t _CK.AVG(Max) + _JIT.PER(Max)
ps
t_CH.ABS Clock high-pulse width
t t t t t _CH.AVG(Min) x _CK.AVG(Min) + _{JIT.DUTY(Min) CH.AVG(Max)} x _CK.AVG(Max) +
ps
t_{JIT.DUTY(Max)}
t_CL.ABS Clock low-pulse width
t t t t t _CL.AVG(Min) x _CK.AVG(Min) + _{JIT.DUTY(Min) CL.AVG(Max)} x _CK.AVG(Max) +
ps
t_{JIT.DUTY(Max)}
Example: for DDR2-667, tCH.ABS(Min) = (0.48 x 3000ps) – 125 ps = 1315 ps = 0.438 x 3000 ps.
Table 59 shows clock-jitter specifications.
Symbol
t_CK.AVG
t_JIT.PER
t_JIT(PER,LCK)
t_JIT.CC
t_JIT(CC,LCK)
t_ERR.2PER
t_ERR.3PER
t_ERR.4PER
t_ERR.5PER
t_ERR(6-10PER)
t_{ERR(11-50PER)}
t_CH.AVG
t_CL.AVG
t_JIT.DUTY
Parameter
TABLE 59
Clock-Jitter Specifications for –667 and –800
DDR2 -667
DDR2 -800
Unit
Min.
Average clock period nominal w/o jitter
3000
Clock-period jitter
–125
Clock-period jitter during DLL locking period –100
Cycle-to-cycle clock-period jitter
–250
Cycle-to-cycle clock-period jitter during DLL- –200
locking period
Cumulative error across 2 cycles
–175
Cumulative error across 3 cycles
–225
Cumulative error across 4 cycles
–250
Cumulative error across 5 cycles
–250
Cumulative error across n cycles with n = 6 .. –350
10, inclusive
Cumulative error across n cycles with n = 11 .. –450
50, inclusive
Average high-pulse width
0.48
Average low-pulse width
0.48
Duty-cycle jitter
–125
Max.
8000
+125
+100
+250
+200
+175
+225
+250
+250
+350
+450
0.52
0.52
+125
Min.
2500
–100
–80
–200
–160
–150
–175
–200
–200
–300
–450
0.48
0.48
–100
Max.
8000
+100
+80
+200
+160
+150
+175
+200
+200
+300
+450
0.52
0.52
+100
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
t_CK.AVG
t_CK.AVG
ps
Rev. 1.3, 2007-07
63
03062006-ZNH8-HURV